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THEORY OF OPERATION

1st

SW-CAP

Integrator

Analog

In

X(z)

+

−

+

−

2nd

SW-CAP

Integrator

3rd

SW-CAP

Integrator

+

−

4th

SW-CAP

Integrator

+

+

+

+

+

+

+

+

5th

SW-CAP

Integrator

Digital

Out

Y(z)

Comparator

Qn(z)

H(z)

1-Bit

DAC

STF(z) = H(z) / [1 + H(z)]

NTF(z) = 1 / [1 + H(z)]

Y(z) = STF(z) * X(z) + NTF(z) * Qn(z)

Signal Transfer Function

Noise Transfer Function

B0005-01

SYSTEM CLOCK

PCM1801

SBAS131C – OCTOBER 2000 – REVISED JULY 2007

The PCM1801 consists of a band-gap reference, two channels of a single-to-differential converter, a fully

differential 5th-order delta-sigma modulator, a decimation filter (including digital high-pass), and a serial interface

circuit. The block diagram illustrates the total architecture of the PCM1801, and the analog front-end diagram

illustrates the architecture of the single-to-differential converter and the antialiasing filter. Figure 22 illustrates the

architecture of the 5th-order delta-sigma modulator and transfer functions.

An internal high-precision reference with two external capacitors provides all reference voltages which are

required by the converter, and defines the full-scale voltage range of both channels. The internal single-ended to

differential voltage converter saves the design, space, and extra parts needed for external circuitry required by

many delta-sigma converters. The internal full-differential architecture provides a wide dynamic range and

excellent power-supply rejection performance.

The input signal is sampled at a 64

× oversampling rate, eliminating the need for a sample-and-hold circuit and

simplifying antialias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integrators

which use a switched-capacitor topology, a comparator, and a feedback loop consisting of a 1-bit

digital-to-analog converter (DAC). The delta-sigma modulator shapes the quantization noise, shifting it out of the

audio band in the frequency domain. The high order of the modulator enables it to randomize the modulator

outputs, reducing idle tone levels.

The 64-fS, 1-bit stream from the modulator is converted to 1-fS, 16-bit digital data by the decimation filter, which

also acts as a low-pass filter to remove the shaped quantization noise. The dc components are removed by a

digital high-pass filter, and the filtered output is converted to time-multiplexed serial signals through a serial

interface which provides flexible serial formats.

Figure 22. Simplified Diagram of the PCM1801 5th-Order Delta-Sigma Modulator

The system clock for the PCM1801 must be either 256 fS, 384 fS, or 512 fS, where fS is the audio sampling

frequency. The system clock must be supplied on SCKI (pin 5).

The PCM1801 also has a system clock detection circuit that automatically senses if the system clock is

operating at 256 fS, 384 fS, or 512 fS.

When a 384-fS or 512-fS system clock is used, the PCM1801 automatically divides the clock down to 256 fS

internally. This 256-fS clock is used to operate the digital filter and the modulator. Table 2 lists the relationship of

typical sampling frequencies and system clock frequencies. Figure 23 illustrates the system clock timing.

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