32/fS

48/f

in or 48/fS

Fade-In Start

Fade-In Complete

DOUT

DOUT

(Contents)

Normal Data

Synchronization Lost

Synchronous

1/f

S

BPZ

State of

Synchronization

Asynchronous

Synchronous

Resynchronization

Synchronization Lost

Asynchronous

Resynchronization

Synchronous

Normal Data

Undefined

Data

Normal Data

Zero Data

Zero Data

Normal Data

Fade-In Restart

32/f

S

48/f

in or 48/fS

PCM1808

www.ti.com

SLES177B – APRIL 2006 – REVISED AUGUST 2015

Feature Description (continued)

Table 1. Sampling Frequency and System Clock Frequency (continued)

SAMPLING FREQUENCY (kHz)

SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)

256 fS

384 fS

512 fS

48

12.288

18.432

24.576

64

16.384

24.576

32.768

88.2

22.5792

33.8688

45.1584

96

24.576

36.864

49.152

7.3.3 Synchronization With Digital Audio System

In slave mode, the PCM1808 device operates under LRCK (pin 7), synchronized with system clock SCKI (pin 6).

The PCM1808 device does not require a specific phase relationship between LRCK and SCKI, but does require

the synchronization of LRCK and SCKI.

If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 BCK/frame (±5 BCKs for 48

BCK/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1 / fS

and digital output goes to zero data (BPZ code) until resynchronization between LRCK and SCKI occurs.

In the case of changes less than ±5 BCKs for 64 BCK/frame (±4 BCKs for 48 BCK/frame), resynchronization

does not occur, and the previously described digital output control and discontinuity do not occur.

Figure 23 illustrates the digital output response for loss of synchronization and resynchronization. During

undefined data, the PCM1808 device can generate some noise in the audio signal. Also, the transition of normal

data to undefined data creates a discontinuity in the digital output data, which can generate some noise in the

audio signal. The digital output is valid after resynchronization completes and the time of 32 / fS has elapsed.

Because the fade-in operation is performed, it takes additional time of 48 / fin or 48 / fS to obtain the level

corresponding to the analog input signal. In the case of loss of synchronization during the fade-in or fade-out

operation, the operation stops and DOUT (pin 9) goes to zero data immediately. The fade-in operation resumes

from mute after the time of 32 / fS following resynchronization.

Figure 23. ADC Digital Output for Loss of Synchronization and Resynchronization

Copyright © 2006–2015, Texas Instruments Incorporated

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