PCM1808

SLES177B – APRIL 2006 – REVISED AUGUST 2015

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Device Functional Modes (continued)

7.4.2 Clock-Halt Power-Down and Reset Function

The PCM1808 device has a power-down and reset function. Halting SCKI (pin 6) in both master and slave

modes triggers this function. The function is available any time after power on. Reset and power down occur

automatically 4

μs (minimum) after the halt of SCKI. During assertion of the clock-halt reset, the PCM1808

device stays in the reset and power-down mode, with DOUT (pin 9) forced to zero. Release the reset and power-

down mode requires the supply of SCKI. The digital output is valid after release of the reset state and elapse of

the time of 1024 SCKI + 8960 / fS. Performing the fade-in operation takes additional time of 48 / fin or 48 / fS to

attain the level corresponding to the analog input signal. Figure 3 illustrates the clock-halt reset timing.

To avoid ADC performance degradation, BCK (pin 8) and LRCK (pin 7) must synchronize with SCKI within 4480

/ fS after the resumption of SCKI. If it takes more than 4480 / fS for BCK and LRCK to synchronize with SCKI,

mask SCKI until it again achieves synchronization, taking care of glitch and jitter. See the typical circuit

connection diagram, Figure 26.

To avoid ADC performance degradation, assertion of the clock-halt reset is necessary when changing system

clock SCKI or the audio interface clocks BCK and LRCK (sampling rate fS) on the fly.

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