Host

Device

(1)

Device

(2)

Device

(N)

RX

TX

Interface Logic

Interface Logic

Interface Logic

RX

RX

RX

TX

TX

TX

I/O

Control

Interface

RX

TX

Temperature

Register

Configuration

Register

T

LOW

Register

T

HIGH

Register

Command

Register

8

TMP104

SBOS564B – NOVEMBER 2011 – REVISED DECEMBER 2018

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The TMP104 supports unique address assignment and alert interrupt procedures. There are general-call read

and write commands that allow simultaneous reads or writes to all devices in the daisy-chain. The interface has

built-in time-outs (typically 28 ms) that return the interface to a known state if communication is disrupted.

7.3.2 Command Register

Figure 8 shows the internal register structure of the TMP104. Communications between the registers are

transferred through the interface in LSB-first order. The 8-bit Command Register, as shown in Table 3, is used to

determine the type of instruction being addressed. These eight bits could either interpret a global instruction or

an individual instruction, which is determined by the value of P7. When P7 = 0, the command byte interprets an

individual instruction; when P7 = 1, the command byte interprets a global instruction.

Figure 8. Internal Register Structure

Table 3. Command Register Byte

P7

P6

P5

P4

P3

P2

P1

P0

GLB

IN3/ID3

IN2/ID2

IN1/ID1

IN0/ID0

P1

P0

R/W

7.3.3 Global Initialization and Address Assignment Sequence

At device power-up, every TMP104 in the daisy-chain is connected in transparent mode, as shown in Figure 9.

The host must send the initialization command (P7-P0 = 10001100) in order for the bus to program its internal

address depending on the number of devices on the bus.

Figure 9. TMP104 Daisy-Chain: Bus Status at Start of Global Initialization