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ADC14155QML-SP

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SNAS378L – NOVEMBER 2008 – REVISED FEBRUARY 2019

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Copyright © 2008–2019, Texas Instruments Incorporated

7.3.3.1 Clock Inputs

The CLK+ and CLK– signals control the timing of the sampling process. The CLK_SEL/DF pin (pin 8) allows the

user to configure the ADC for either differential or single-ended clock mode (see Clock Mode Select/Data Format

(CLK_SEL/DF)). In differential clock mode, the two clock signals should be exactly 180° out of phase from each

other and of the same amplitude. In the single-ended clock mode, the clock signal should be routed to the CLK+

input and the CLK– input should be tied to AGND in combination with the correct setting from Table 4.

To achieve the optimum noise performance, the clock inputs should be driven with a stable, low jitter clock

signal. The clock input signal should also have a short transition region. This can be achieved by passing a low-

jitter sinusoidal clock source through a high speed buffer gate. This configuration is shown in Figure 24. The

trace carrying the clock signal should be as short as possible and should not cross any other signal line, analog

or digital, not even at 90°. Figure 24 shows the recommended clock input circuit.

The clock signal also drives an internal state machine. If the clock is interrupted, or its frequency is too low, the

charge on the internal capacitors can dissipate to the point where the accuracy of the output data will degrade.

This will limit the minimum sample rate.

The clock line should be terminated at its source in the characteristic impedance of that line. Care should be

taken to maintain a constant clock line impedance throughout the length of the line. Refer to Application Note

AN-905 (SNLA035) for information on setting characteristic impedance.

It is highly desirable that the source driving the ADC clock pins only drive that pin. However, if that source is

used to drive other devices, then each driven pin should be AC terminated with a series RC to ground, such that

the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is

(3)

where tPD is the signal propagation rate down the clock line, "L" is the line length and ZO is the characteristic

impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it

as seen from the clock source. Typical tPD is about 150 ps/in (60 ps/cm) on FR-4 board material. The units of "L"

and tPD should be the same (inches or centimeters).

The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise

duty cycle is difficult, the ADC14155 has a Duty Cycle Stabilizer. It is designed to maintain performance over a

clock duty cycle range of 30% to 70%.

7.3.3.2 Power-Down (PD)

Power-down can be enabled through this two-state input pin. Table 3 shows how to power-down the ADC14155.

Table 3. Power Down Selection Table

PD Input Voltage

Power State

VA

Power-down

AGND

On

The power-down mode allows the user to conserve power when the converter is not being used. In the power-

down state all bias currents of the analog circuitry, excluding the reference are shut down which reduces the

power consumption to 5 mW with no clock running. The output data pins are undefined and the data in the

pipeline is corrupted while in the power-down mode.

The Power-down Mode Exit Cycle time is determined by the value of the capacitors on the VRP (pin 42, 43), VRM

(pin 46, 47) and VRN (pin 44, 45) reference bypass pins (pins 43, 44 and 45) and is approximately 3 ms with the

recommended component values. These capacitors lose their charge in the power-down mode and must be

recharged by on-chip circuitry before conversions can be accurate. Smaller capacitor values allow slightly faster

recovery from the power down mode, but can result in a reduction in SNR, SINAD and ENOB performance.