ADC14155HCVAL datasheet(5/36 Pages) TI2

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DRGND

VDR

DGND

AGND

ADC14155QML-SP

www.ti.com

SNAS378L – NOVEMBER 2008 – REVISED FEBRUARY 2019

Product Folder Links: ADC14155QML-SP

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Pin Descriptions and Equivalent Circuits (continued)

PIN NO.

SYMBOL

EQUIVALENT CIRCUIT

DESCRIPTION

CLK_SEL/DF

This is a four-state pin controlling the input clock mode and output

data format.

CLK_SEL/DF = VA, CLK+ and CLK– are configured as a differential

clock input. The output data format is 2's complement.

CLK_SEL/DF = (2 / 3) * VA, CLK+ and CLK– are configured as a

differential clock input. The output data format is offset binary.

CLK_SEL/DF = (1 / 3) * VA, CLK+ is configured as a single-ended

clock input and CLK– should be tied to AGND. The output data

format is 2's complement.

CLK_SEL/DF = AGND, CLK+ is configured as a single-ended clock

input and CLK– should be tied to AGND. The output data format is

offset binary.

This is a two-state input controlling Power Down.

PD = VA, Power Down is enabled. In the Power Down state only the

reference voltage circuitry remains active and power dissipation is

reduced.

PD = AGND, Normal operation.

17-24,

27-32

D0–D13

Digital data output pins that make up the 14-bit conversion result. D0

(pin 17) is the LSB, while D13 (pin 32) is the MSB of the output

word. Output levels are CMOS compatible.

OVR

Over-Range Indicator. This output is set HIGH when the input

amplitude exceeds the 14-bit conversion range (0 to 16383).

DRDY

Data Ready Strobe. This pin is used to clock the output data. It has

the same frequency as the sampling clock. One word of data is

output in each cycle of this signal. The rising edge of this signal

should be used to capture the output data.

ANALOG POWER

2, 9, 37, 40,

Positive analog supply pins. These pins should be connected to a

quiet 3.3-V source and be bypassed to AGND with 100-pF and 0.1-

µF capacitors located close to the power pins.

1, 3, 6, 10,

38, 39

AGND

The ground return for the analog supply.

DIGITAL POWER

Positive digital supply pin. This pin should be connected to a quiet

3.3-V source and be bypassed to DGND with a 100-pF and 0.1-µF

capacitor located close to the power pin.

DGND

The ground return for the digital supply.

16, 25, 26,

VDR

Positive driver supply pin for the output drivers. This pin should be

connected to a quiet voltage source of 1.8 V and be bypassed to

DRGND with 100-pF and 0.1-µF capacitors located close to the

power pins.

15, 35

DRGND

The ground return for the digital output driver supply. These pins

should be connected to the system digital ground. See Layout

Guidelines (Layout and Grounding) for more details.

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