AFE5803ZCF datasheet(44/53 Pages) TI2

44 / 53 page

FPGA Clock/

NoisyClock

n×(20~65)MHz

TIJitterCleaner

CDCE72010/

CDCM7005

CDCLVP1208

1-to-8

CLKBuffer

20~65MHz

ADCCLK

8 Synchronized

ADCCLKs

CDCE72010has10

outputsthusthebuffer

maynotbeneededfor

64CHsystems

B0437-01

AFE5803

SLOS763A

– JANUARY 2012 – REVISED JANUARY 2012

www.ti.com

ADC OPERATION

ADC Clock Distribution

To ensure that the aperture delay and jitter are the same for all channels, the AFE5803 uses a clock tree

network to generate individual sampling clocks for each channel. The clock, for all the channels, are matched

from the source point to the sampling circuit of each of the eight internal ADCs. The variation on this delay is

described in the aperture delay parameter of the output interface timing. Its variation is given by the aperture jitter

number of the same table.

Figure 75. ADC Clock Distribution Network

In the single-end case, it is recommended that the use of low jitter square signals (LVCMOS levels, 1.8 V

amplitude). See TI document SLYT075 for further details on the theory.

The jitter cleaner CDCM7005 or CDCE72010 is suitable to generate the AFE5803

’s ADC clock and ensure the

performance for the14 bit ADC with 77 dBFS SNR. A clock distribution network is shown in Figure 75.

The AFE5803 can accept differential LVDS, LVPECL, and other differential clock inputs as well as single-ended

clock. AC coupling is required between clock drivers and the AFE5803 clock inputs. When single-ended clock is

used, CLKM should be tied to ground. Common clock configurations are illustrated in Figure 76. Appropriate

termination is recommended to achieve good signal integrity.

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AFE5803ZCF Datasheet(PDF) 44 Page - Texas Instruments