AFE5803ZCF datasheet(45/53 Pages) TI2

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S0503-01

(a) LVPECL Configuration

(d) CMOS Configuration

(b) LVDS Configuration

CMOS CLK

Driver

AFE

CMOS CLK

CMOS

AFE

CLOCKs

CLOCK

SOURCE

0.1 F

CDCE72010

AFE

CLOCKs

100

LVDS

0.1 F

CDCM7005

CDCE72010

AFE

CLOCKs

130

LVPECL

0.1 F

3.3 V

130

AFE5803

www.ti.com

SLOS763A

– JANUARY 2012 – REVISED JANUARY 2012

Figure 76. Clock Configurations

Special considerations should be applied in such a clock distribution network design. In typical ultrasound

systems, it is preferred that all clocks are generated from a same clock source, such as CW clocks, audio ADC

clocks, RF ADC clock, pulse repetition frequency signal, frame clock and etc. By doing this, interference due to

clock asynchronization can be minimized.

ADC Reference Circuit

The ADC

’s voltage reference can be generated internally or provided externally. When the internal reference

mode is selected, the REFP/M becomes output pins and should be floated. When 3[15] =1 and 1[13]=1, the

device is configured to operate in the external reference mode in which the VREF_IN pin should be driven with a

1.4V reference voltage and REFP/M must be left open. Since the input impedance of the VREF_IN is high, no

special drive capability is required for the 1.4V voltage reference

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