AFE5803ZCF datasheet(47/53 Pages) TI2

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Buffer

Amp

Rint/Rext

CH7/8_BUFFER_OUTM

CH7/8_BUFFER_OUTP

CH7/8_TEST_OUTM

CH7/8_TEST_OUTP

PGA CH7/8P

PGA CH7/8M

5 kW

AFE5803

www.ti.com

SLOS763A

– JANUARY 2012 – REVISED JANUARY 2012

This fast wake-up response is desired for portable ultrasound applications in which the power saving is critical.

The pulse repetition frequency of a ultrasound system could vary from 50KHz to 500Hz, while the imaging depth

(i.e., the active period for a receive path) varies from 10

μs to hundreds of us. The power saving can be pretty

significant when a system

’s PRF is low. In some cases, only the VCA would be powered down while the ADC

keeps running normally to ensure minimal impact to FPGAs.

In the partial power-down mode, the AFE5803 typically dissipates only 26mW/ch, representing an 80% power

reduction compared to the normal operating mode. This mode can be set using either pins (PDN_VCA and

PDN_ADC) or register bits (VCA_PARTIAL_PDN and ADC_PARTIAL_PDN).

Complete Power-Down Mode

To achieve the lowest power dissipation of 0.7 mW/CH, the AFE5803 can be placed into a complete power-down

mode. This mode is controlled through the registers ADC_COMPLETE_PDN, VCA_COMPLETE_PDN or

PDN_GLOBAL pin. In the complete power-down mode, all circuits including reference circuits within the

AFE5803 are powered down; and the capacitors connected to the AFE5803 are discharged. The wake-up time

depends on the time needed to recharge these capacitors. The wake-up time depends on the time that the

AFE5803 spends in shutdown mode. 0.1

μF at INP and 15 nF at INM can give a wake-up time close to 2.5ms.

VCA TEST MODES

The AFE5803 includes multiple test modes to accelerate system development. The ADC test modes have been

discussed in the register description section.

The VCA has a test mode in which the CH7 and CH8 PGA outputs can be brought. By monitoring these PGA

outputs, the functionality of VCA operation can be verified. Some registers are related to this test mode. PGA

Test Mode Enable: Reg59[9]; Buffer Amplifier Power Down Reg59[8]; and Buffer Amplifier Gain Control

Reg54[4:0].

The PGA outputs are connected to the virtual ground pins of the buffer amplifier through 5 k

Ω resistors. The PGA

outputs can be monitored at the buffer amplifier outputs when the buffer amplifer is enabled. Note that the

signals at the buffer amplifier outputs are attenuated due to the 5K

Ω resistors. The attenuation coefficient is

RINT/EXT/5kΩ. See Table 7 for the RINT configuration.

An alternative way is to measure the PGA outputs directly at the CH8_TEST_OUTM/P and CH7_TEST_OUTM/P

when the buffer amplifier is powered down.

Based on the buffer amplifier configuration, the registers can be set in different ways:

Configuration 1:

In this configuration, the test outputs can be monitored at CH7/8_TEST_OUTP/M

Reg59[9]=1 ;Test mode enabled

Reg59[8]=0 ;Buffer amplifier powered down

Configuration 2:

In this configuration, the test outputs can be monitored at CH7/8_BUFFER_OUTP/M

Reg59[9]=1 ;Test mode enabled

Reg59[8]=1 ;Buffer amplifier powered on

Reg54[4:0]=10H; Internal feedback 2K resistor enabled. Different values can be used as well

Figure 77. AFE5803 PGA Test Mode

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