CC2564C datasheet(28/58 Pages) TI2

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TX digital data

RX digital data

Digital

Demodulation

Amplitude

Phase

ADPLL

Filter

ADC

IFA

LNA

Transmitter path

Receiver path

SWRS092-005

DPA

CC2564C

SWRS199B – APRIL 2016 – REVISED JUNE 2020

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Detailed Description

6.4

Functional Blocks

6.4.1

TheCC2564C device is the third generation of Bluetooth single-chip devices using DRP architecture from

TI. Modifications and new features added to the DRP further improve radio performance.

Figure 6-9 shows the DRP block diagram.

Figure 6-9. DRP Block Diagram

6.4.1.1

Receiver

The receiver uses near-zero-IF architecture to convert the RF signal to baseband data. The signal

received from the external antenna is input to a single-ended low-noise amplifier (LNA) and passed to a

mixer that downconverts the signal to IF, followed by a filter and amplifier. The signal is then quantized by

a sigma-delta analog-to-digital converter (ADC) and further processed to reduce the interference level.

The demodulator digitally downconverts the signal to zero-IF and recovers the data stream using an

adaptive-decision mechanism. The demodulator includes EDR processing with:

•

State-of-the-art performance

•

A maximum-likelihood sequence estimator (MLSE) to improve the performance of basic-rate GFSK

sensitivity

•

Adaptive equalization to enhance EDR modulation

New features include:

•

LNA input range narrowed to increase blocking performance

•

Active spur cancellation to increase robustness to spurs

CC2564C Datasheet(PDF) 28 Page - Texas Instruments

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