CC2564C datasheet(32/58 Pages) TI2

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CC2564C

SWRS199B – APRIL 2016 – REVISED JUNE 2020

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Detailed Description

6.4.3.1

Hardware Interface

The interface includes four signals:

•

Clock: configurable direction (input or output)

•

Frame_Sync and Word_Sync: configurable direction (input or output)

•

Data_In: input

•

Data_Out: output or tri-state signal

The CC2564C device can be the master of the interface when generating the Clock and Frame_Sync

signals or the slave when receiving these two signals.

For slave mode, clock input frequencies of up to 15 MHz are supported. At clock rates above 12 MHz, the

maximum data burst size is 32 bits.

For master mode, the device can generate any clock frequency from 64 kHz to 4.096 MHz.

6.4.3.2

I2S

When the codec interface is configured to support the I2S protocol, these settings are recommended:

•

Bidirectional, full-duplex interface

•

Two time slots per frame: time slot 0 for the left channel audio data; and time slot 1 for the right

channel audio data

•

The length of each time slot is configurable up to 40 serial clock cycles, and the length of the frame is

configurable up to 80 serial clock cycles

6.4.3.3

Data Format

The data format is fully configurable:

•

The data length can be from 8 to 320 bits in 1-bit increments when working with 2 channels, or up to

640 bits when working with 1 channel. The data length can be set independently for each channel.

•

The data position within a frame is also configurable within 1 clock (bit) resolution and can be set

independently (relative to the edge of the Frame_Sync signal) for each channel.

•

The Data_In and Data_Out bit order can be configured independently. For example; Data_In can start

with the most significant bit (MSB); Data_Out can start with the least significant bit (LSB). Each

channel is separately configurable. The inverse bit order (that is, LSB first) is supported only for

sample sizes up to 24 bits.

•

Data_In and Data_Out are not required to be the same length.

•

The Data_Out line is configured to Hi-Z output between data words. Data_Out can also be set for

permanent Hi-Z output, regardless of the data output. This configuration allows the device to be a bus

slave in a multislave PCM environment. At power up, Data_Out is configured as Hi-Z output.

6.4.3.4

Frame-Idle Period

The codec interface handles frame-idle periods, during which the clock pauses and becomes 0 at the end

of the frame after all data are transferred.

The device supports frame-idle periods both as master and slave of the codec bus.

When the device is the master of the interface, the frame-idle period is configurable. There are two

configurable parameters:

•

Clk_Idle_Start: indicates the number of clock cycles from the beginning of the frame to the beginning of

the frame-idle period. After Clk_Idle_Start clock cycles, the clock becomes 0.

•

Clk_Idle_End: indicates the time from the beginning of the frame to the end of the frame-idle period.

The time is given in multiples of clock periods.

The delta between Clk_Idle_Start and Clk_Idle_End is the clock idle period.

For example, for clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60, Clk_Idle_End = 90.

CC2564C Datasheet(PDF) 32 Page - Texas Instruments

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