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ISO7840, ISO7840F

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SLLSEN2B – JULY 2015 – REVISED APRIL 2016

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Copyright © 2015–2016, Texas Instruments Incorporated

(1)

Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care

should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on

the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.

Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.

(2)

This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by

means of suitable protective circuits.

(3)

Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4)

Apparent charge is electrical discharge caused by a partial discharge (pd).

(5)

All pins on each side of the barrier tied together creating a two-pin device.

6.6 Insulation Specifications

PARAMETER

TEST CONDITIONS

SPECIFICATION

UNIT

DW

DWW

GENERAL

CLR

External clearance(1)

Shortest pin-to-pin distance through air

>8

>14.5

mm

CPG

External creepage(1)

Shortest pin-to-pin distance across the package

surfaceHigh Voltage Feature Description

>8

>14.5

mm

DTI

Distance through the insulation

Minimum internal gap (internal clearance)

>21

>21

μm

CTI

Comparative tracking index

DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A

>600

>600

V

Material group

I

I

Overvoltage category per IEC

60664-1

Rated mains voltage

≤ 600 VRMS

I–IV

I–IV

Rated mains voltage

≤ 1000 VRMS

I–III

I–IV

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(2)

VIORM

Maximum repetitive peak isolation

voltage

2121

2828

VPK

VIOWM Maximum isolation working voltage

AC voltage (sine wave); Time dependent dielectric

breakdown (TDDB) Test, see Figure 1 and Figure 2

1500

2000

VRMS

DC voltage

2121

2828

VDC

VIOTM

Maximum transient isolation

voltage

VTEST = VIOTM

t = 60 s (qualification)

t= 1 s (100% production)

8000

8000

VPK

VIOSM

Maximum surge isolation voltage(3)

Test method per IEC 60065, 1.2/50 µs waveform,

VTEST = 1.6 × VIOSM = 12800 VPK (qualification)

8000

8000

VPK

qpd

Apparent charge(4)

Method a: After I/O safety test subgroup 2/3,

Vini = VIOTM, tini = 60 s;

Vpd(m) = 1.2 × VIORM = 2545 VPK (DW) and 3394 VPK

(DWW), tm = 10 s

≤5

≤5

pC

Method a: After environmental tests subgroup 1,

Vini = VIOTM, tini = 60 s;

Vpd(m) = 1.6 × VIORM = 3394 VPK (DW) and 4525 VPK

(DWW), tm = 10 s

≤5

≤5

Method b1: At routine test (100% production) and

preconditioning (type test)

Vini = VIOTM, tini = 1 s;

Vpd(m) = 1.875 × VIORM = 3977 VPK (DW) and 5303 VPK

(DWW), tm = 1 s

≤5

≤5

CIO

Barrier capacitance, input to

output(5)

VIO = 0.4 × sin (2πft), f = 1 MHz

2

2

pF

RIO

Isolation resistance, input to

output(5)

VIO = 500 V, TA = 25°C

>1012

>1012

Ω

VIO = 500 V, 100°C ≤ TA ≤ 125°C

>1011

>1011

VIO = 500 V at TS = 150°C

>109

>109

Pollution degree

2

2

Climatic category

55/125/21

55/125/21

UL 1577

VISO

Withstand isolation voltage

VTEST = VISO = 5700 VRMS, t = 60 s (qualification),

VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100%

production)

5700

5700

VRMS