LMH0318 datasheet(49/59 Pages) TI2

49 / 59 page

LMH0318

www.ti.com

SNLS508 – SEPTEMBER 2015

11 Layout

11.1 Layout Guidelines

The following guidelines should be followed when designing the layout:

1. Set trace impedances to 75

Ω ± 5% single ended, 100 Ω ± 5% differential.

2. Maintain the same signal reference plane for 75

Ω single-end trace, and reference plane for 100 Ω

differential traces.

3. Use the smallest size surface mount components.

4. Use solid planes. Provide GND or VDD relief under the component pads to minimize parasitic capacitance.

5. Select trace widths that minimize the impedance mismatch along the signal path.

6. Select a board stack-up that supports 75

Ω or 50 Ω single-end trace, 100 Ω coupled differential traces.

7. Use surface mount ceramic capacitors.

8. Place return loss network as close to the device as possible.

9. Maintain symmetry on the complimentary signals.

10. Route 100

Ω traces uniformly (keep trace widths and trace spacing uniform along the trace).

11. Avoid sharp bends; use 45-degree or radial bends.

12. Walk along the signal path, identify geometry changes and estimate their impedance changes.

13. Maintain 75

Ω impedance with a well-designed connectors’ footprint.

14. Consult a 3-D simulation tool to guide layout decisions.

15. Use the shortest path for VDD and Ground hook-ups; connect pin to planes with vias to minimize or

eliminate trace.

16. When a high speed trace changes layer, provide at least 2 return vias to improve current return path.

11.2 Layout Example

The following example layout demonstrates how the thermal pad should be laid out using standard WQFN board

routing guidelines.

Note: Thermal pad is divided into 4 squares with solder paste

Figure 22. LMH0318 Recommended Four Squares Solder Paste

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LMH0318 Datasheet(PDF) 49 Page - Texas Instruments