SM73201

www.ti.com

SNOSB89B – JUNE 2011 – REVISED JUNE 2013

Burst Mode Operation

Normal operation of the SM73201 requires the SCLK frequency to be 20 times the sample rate and the CS rate

to be the same as the sample rate. However, in order to minimize power consumption in applications requiring

sample rates below 250 kSPS, the SM73201 should be run with an SCLK frequency of 5 MHz and a CS rate as

slow as the system requires. When this is accomplished, the SM73201 is operating in burst mode. The SM73201

enters into acquisition mode at the end of each conversion, minimizing power consumption. This causes the

converter to spend the longest possible time in acquisition mode. Since power consumption scales directly with

conversion rate, minimizing power consumption requires determining the lowest conversion rate that will satisfy

the requirements of the system.

PCB LAYOUT AND CIRCUIT CONSIDERATIONS

For best performance, care should be taken with the physical layout of the printed circuit board. This is especially

true with a low VREF or when the conversion rate is high. At high clock rates there is less time for settling, so it is

important that any noise settles out before the conversion begins.

Analog and Digital Power Supplies

Any ADC architecture is sensitive to spikes on the power supply, reference, and ground pins. These spikes may

originate from switching power supplies, digital logic, high power devices, and other sources. Power to the

SM73201 should be clean and well bypassed. A 0.1 µF ceramic bypass capacitor and a 1 µF to 10 µF capacitor

should be used to bypass the SM73201 supply, with the 0.1 µF capacitor placed as close to the SM73201

package as possible.

Since the SM73201 has both the VA and VIO pins, the user has three options on how to connect these pins. The

first option is to tie VA and VIO together and power them with the same power supply. This is the most cost

effective way of powering the SM73201 but is also the least ideal. As stated previously, noise from VIO can

couple into VA and adversely affect performance. The other two options involve the user powering VA and VIO

with separate supply voltages. These supply voltages can have the same amplitude or they can be different. VA

can be set to any value between +4.5V and +5.5V; while VIO can be set to any value between +2.7V and +5.5V.

Best performance will typically be achieved with VA operating at 5V and VIO at 3V. Operating VA at 5V offers the

best linearity and dynamic performance when VREF is also set to 5V; while operating VIO at 3V reduces the power

consumption of the digital logic. Operating the digital interface at 3V also has the added benefit of decreasing the

noise created by charging and discharging the capacitance of the digital interface pins.

Voltage Reference

The reference source must have a low output impedance and needs to be bypassed with a minimum capacitor

value of 0.1 µF. A larger capacitor value of 1 µF to 10 µF placed in parallel with the 0.1 µF is preferred. While the

SM73201 draws very little current from the reference on average, there are higher instantaneous current spikes

at the reference.

VREF of the SM73201, like all A/D converters, does not reject noise or voltage variations. Keep this in mind if

VREF is derived from the power supply. Any noise and/or ripple from the supply that is not rejected by the external

reference circuitry will appear in the digital results. The use of an active reference source is recommended. The

LM4040 and LM4050 shunt reference families and the SM74601, LM4120, and LM4140 series reference families

are excellent choices for a reference source.

PCB Layout

Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor

performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as

short as possible. Digital circuits create substantial supply and ground current transients. The logic noise

generated could have significant impact upon system noise performance. To avoid performance degradation of

the SM73201 due to supply noise, avoid using the same supply for the VA and VREF of the SM73201 that is used

for digital circuitry on the board.

Copyright © 2011–2013, Texas Instruments Incorporated

Submit Documentation Feedback

21

Product Folder Links: SM73201