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SM73201 Datasheet(PDF) 8 Page - Texas Instruments |
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SM73201 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 31 page ![]() SM73201 SNOSB89B – JUNE 2011 – REVISED JUNE 2013 www.ti.com Specification Definitions APERTURE DELAY is the time between the first falling edge of SCLK and the time when the input signal is sampled for conversion. COMMON MODE REJECTION RATIO (CMRR) is a measure of how well in-phase signals common to both input pins are rejected. To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed from 2V to 3V. CMRR = 20 LOG ( Δ Common Input / Δ Output Offset) CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation from the ideal slope of the transfer function. It is the difference between Positive Full-Scale Error and Negative Full-Scale Error and can be calculated as: Gain Error = Positive Full-Scale Error − Negative Full-Scale Error INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from ½ LSB below the first code transition through ½ LSB above the last code transition. The deviation of any given code from this straight line is measured from the center of that code value. MISSING CODES are those output codes that will never appear at the ADC outputs. The SM73201 is specified not to have any missing codes. NEGATIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions from code 0x8001h to 0x8000h and −VREF + 1 LSB. NEGATIVE GAIN ERROR is the difference between the negative full-scale error and the offset error. OFFSET ERROR is the difference between the differential input voltage at which the output code transitions from code 0x0000h to 0x0001h and 1 LSB. POSITIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions from code 0xFFFEh to 0xFFFFh and VREF - 1 LSB. POSITIVE GAIN ERROR is the difference between the positive full-scale error and the offset error. POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well a change in the analog supply voltage is rejected. PSRR is calculated from the ratio of the change in offset error for a given change in supply voltage, expressed in dB. For the SM73201, VA is changed from 4.5V to 5.5V. PSRR = 20 LOG ( ΔOutput Offset / ΔVA) SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below one-half the sampling frequency, including harmonics but excluding d.c. 8 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SM73201 |
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