1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

5V_SUPPLY

LV_SUPPLY

GND

TMDS_D2+

TMDS_GND

TMDS_D2–

TMDS_D1+

TMDS_GND

TMDS_D1–

TMDS_D0+

TMDS_GND

TMDS_D0–

TMDS_CK+

TMDS_GND

TMDS_CK–

CE_REMOTE_IN

DDC_CLK_IN

DDC_DAT_IN

HOTPLUG_DET_IN

5V_OUT

ESD_BYP

GND

TMDS_D2+

TMDS_GND

TMDS_D2–

TMDS_D1+

TMDS_GND

TMDS_D1–

TMDS_D0+

TMDS_GND

TMDS_D0–

TMDS_CK+

TMDS_GND

TMDS_CK–

CE_REMOTE_OUT

DDC_CLK_OUT

DDC_DAT_OUT

HOTPLUG_DET_OUT

DBT PACKAGE

(TOP VIEW)

3

TPD12S521

www.ti.com

SLVS639F – OCTOBER 2007 – REVISED FEBRUARY 2016

Product Folder Links: TPD12S521

Submit Documentation Feedback

Copyright © 2007–2016, Texas Instruments Incorporated

6 Pin Configuration and Functions

(1)

Human-Body Model (HBM) per MIL-STD-833, Method 3015, CDISCHARGE = 100 pF, RDISCHARGE = 1.5 kΩ, 5V_SUPPLY and

LV_SUPPLY within recommended operating conitions, GND = 0 V, and ESD_BYP (pin 37) and HOTPLUG_DET_OUT (pin 20) each

bypassed with a 0.1-µF ceramic capacitor connnected to GND.

(2)

Standard IEC 61000-4-2, CDISCHARGE = 150 pF, RDISCHARGE = 330 Ω, 5V_SUPPLY and LV_SUPPLY within recommended operating

conditions, GND = 0 V, and ESD_BYP (pin 37) and HOTPLUG_DET_OUT (pin 20) each bypassed with a 0.1-µF ceramic capacitor

connected to GND.

(3)

These two pins must be connected together inline on the PCB.

(4)

This output can be connected to an external 0.1-µF ceramic capacitor, resulting in an increased ESD withstand voltage rating.

Pin Functions

PIN

TYPE

ESD

DESCRIPTION

NAME

NO.

5V_SUPPLY

1

PWR

2 kV(1)

Current source for 5V_OUT.

LV_SUPPLY

2

Bias for CE/DDC/HOTPLUG level shifters.

GND, TMDS_GND

3, 5, 8, 11,14, 25,

28, 31, 34, 36

GND

NA

TMDS ESD and parasitic GND return.

TMDS_D2+

4, 35

ESD clamp

8 kV(2)

TMDS 0.8-pF ESD protection.(3)

TMDS_D2–

6, 33

TMDS_D1+

7, 32

TMDS_D1–

9, 30

TMDS_D0+

10, 29

TMDS_D0–

12, 27

TMDS_CK+

13, 26

TMDS_CK–

15, 24

CE_REMOTE_IN

16

IO

2 kV(1)

LV_SUPPLY referenced logic level into ASIC.

DDC_CLK_IN

17

DDC_DAT_IN

18

HOTPLUG_DET_IN

19

HOTPLUG_DET_OUT

20

IO, ESD clamp

8 kV(2)

5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD(4) to

connector.

DDC_DAT_OUT

21

5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to

connector.

DDC_CLK_OUT

22

CE_REMOTE_OUT

23

IO, ESD clamp

8 kV(2)

3.3-V_SUPPLY referenced logic level out, plus 3.5-pF ESD to

connector.

ESD_BYP

37

ESD Bypass

2 kV(1)

ESD bypass. This pin must be connected to a 0.1-µF ceramic

capacitor.

5V_OUT

38

PWR

2 kV(1)

5-V regulator output