7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

VDD = 2.5 V to 6 V, IOH = −500 μA

VDD – 0.2

V

VDD = 3.3 V, IOH = −2 μA

VDD – 0.4

VDD = 6 V, IOH = −4 mA

TA = −40°C to +25°C

VDD – 0.4

TA = 125°C

VDD – 0.5

VOL

Low-level output voltage

VDD = 2 V to 6 V, IOL = 500 μA

0.3

V

VDD = 3.3 V, IOL = 2 mA

0.4

VDD = 6 V, IOL = 4 mA

0.4

Power-up reset voltage(1)

VDD ≥ 1.1 V, IOL = 50 μA

0.2

V

VIT−

Negative-going input threshold

voltage(2)

TPS3809J25-Q1

TA = −40°C to +125°C

2.20

2.25

2.30

V

TPS3809L30-Q1

2.58

2.64

2.7

TPS3809K33-Q1

2.87

2.93

2.99

TPS3809I50-Q1

TA = −40°C to +85°C

4.45

4.55

4.65

TA = −40°C to +125°C

4.4

4.55

4.65

Vhys

Hysteresis

TPS3809J25-Q1

30

mV

TPS3809L30-Q1

35

TPS3809K33-Q1

40

TPS3809I50-Q1

60

IDD

Supply current

VDD = 2 V, Output unconnected

9

15

μA

VDD = 6 V, Output unconnected

20

30

Ci

Input capacitance

VI = 0 V to VDD

5

pF

(1)

The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V.

(2)

To ensure best stability of the threshold voltage, a bypass capacitor ( 0.1 µF, ceramic) should be placed near the supply terminals.

7.6 Timing Requirements

RL = 1 MΩ, CL = 50 pF, TA = 25°C

MIN

NOM

MAX

UNIT

tw

Pulse width at VDD

VDD = VIT− + 0.2 V, VDD = VIT− − 0.2 V

10

μs

7.7 Switching Characteristics

RL = 1 MΩ, CL = 50 pF, TA = 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

td

Delay time

VDD ≥ VIT− + 0.2 V, See

timing diagram, Section 7.8

120

200

280

ms

tPHL

Propagation (delay) time,

high-to-low-level output

VDD to RESET delay

VIL = VIT− − 0.2 V, VIH = VIT−

+0.2 V

10

μs

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TPS3809J25-Q1, TPS3809L30-Q1, TPS3809K33-Q1, TPS3809I50-Q1

SGLS142C – DECEMBER 2002 – REVISED DECEMBER 2020

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