DAC7552

SLAS442D

– JANUARY 2005 – REVISED JUNE 2011

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION(1)

SPECIFIED

PACKAGE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

PACKAGE

TEMPERATURE

DESIGNATOR

MARKING

NUMBER

MEDIA

RANGE

DAC7552IRGTT

250-piece Tape and Reel

DAC7552

16 QFN

RGT

–40°C TO 105°C

D752

DAC7552IRGTR

3000-piece Tape and Reel

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

UNIT

VDD , IOVDD to GND

–0.3 V to 6 V

Digital input voltage to GND

–0.3 V to VDD + 0.3 V

VOUT to GND

–0.3 V to VDD+ 0.3 V

Operating temperature range

–40°C to 105°C

Storage temperature range

–65°C to 150°C

Junction temperature (TJ Max)

150

°C

(1)

Stresses above those listed under

“Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute

maximum conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

VDD = 2.7 V to 5.5 V, VREF = VDD, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 105°C, unless otherwise

specified

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

STATIC PERFORMANCE(1)

Resolution

12

Bits

Relative accuracy

±0.35

±1

LSB

Differential nonlinearity

Specified monotonic by design

±0.08

±0.5

LSB

Offset error

±12

mV

Zero-scale error

All zeroes loaded to DAC register

±12

mV

Gain error

±0.15

%FSR

Full-scale error

±0.5

%FSR

Zero-scale error drift

7

µV/°C

Gain temperature coefficient

3

ppm of FSR/

°C

PSRR

VDD = 5 V

0.75

mV/V

(1)

Linearity tested using a reduced code range of 30 to 4065; output unloaded.

2

Copyright

© 2005–2011, Texas Instruments Incorporated