VA

VOUTA

VOUTB

VOUTD

VOUTC

SCLK

DIN

VREFIN

GND

VSSOP

1

2

3

4

5

10

9

8

7

6

SYNC

VA

VOUTA

VOUTB

VOUTD

VOUTC

SCLK

DIN

VREFIN

GND

SON

1

2

3

4

5

10

9

8

7

6

SYNC

3

DAC084S085

www.ti.com

SNAS363F – MAY 2006 – REVISED MARCH 2016

Product Folder Links: DAC084S085

Submit Documentation Feedback

Copyright © 2006–2016, Texas Instruments Incorporated

5 Description

A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a

valid write to the device. A power-down feature reduces power consumption to less than a microWatt with three

different termination options.

The low-power consumption and small packages of the DAC084S085 make it an excellent choice for use in

battery-operated equipment.

The DAC084S085 is one of a family of pin-compatible DACs, including the 10-bit DAC104S085 and the 12-bit

DAC124S085. The DAC084S085 operates over the extended industrial temperature range of

−40°C to +105°C.

6 Pin Configuration and Functions

DSC Package

10-Pin WSON

Top View

DGS Package

10-Pin VSSOP

Top View

Pin Functions

PIN

TYPE

DESCRIPTION

NO.

NAME

1

VA

Supply

Power supply input. Must be decoupled to GND.

2

VOUTA

Analog Output

Channel A Analog Output Voltage.

3

VOUTB

Analog Output

Channel B Analog Output Voltage.

4

VOUTC

Analog Output

Channel C Analog Output Voltage.

5

VOUTD

Analog Output

Channel D Analog Output Voltage.

6

GND

Ground

Ground reference for all on-chip circuitry.

7

VREFIN

Analog Input

Unbuffered reference voltage shared by all channels. Must be decoupled

to GND.

8

DIN

Digital Input

Serial Data Input. Data is clocked into the 16-bit shift register on the

falling edges of SCLK after the fall of SYNC.

9

SYNC

Digital Input

Frame synchronization input for the data input. When this pin goes low, it

enables the input shift register and data is transferred on the falling edges

of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is

brought high before the 16th clock, in which case the rising edge of

SYNC acts as an interrupt and the write sequence is ignored by the DAC.

10

SCLK

Digital Input

Serial Clock Input. Data is clocked into the input shift register on the

falling edges of this pin.

11

PAD

(WSON only)

Ground

Exposed die attach pad can be connected to ground or left floating.

Soldering the pad to the PCB offers optimal thermal performance and

enhances package self-alignment during reflow.