7

DAC084S085

www.ti.com

SNAS363F – MAY 2006 – REVISED MARCH 2016

Product Folder Links: DAC084S085

Submit Documentation Feedback

Copyright © 2006–2016, Texas Instruments Incorporated

Electrical Characteristics (continued)

The following specifications apply for VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range

3 to 252. All limits are at TA = 25°C, unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN(1)

TYP(1)

MAX(1)

UNIT

PPD

Power-down supply power

(output unloaded, SYNC = DIN

= 0 V after PD mode loaded)

All PD Modes(2)

VA = 2.7 V

to 3.6 V

TA = 25°C

0.3

µW

TMIN ≤ TA ≤ TMAX

3.6

VA = 4.5 V

to 5.5 V

TA = 25°C

0.8

µW

TMIN ≤ TA ≤ TMAX

5.5

(1)

Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing

Quality Level).

(2)

This parameter is specified by design and/or characterization and is not tested in production.

7.6 Timing Requirements

Values shown in this table are design targets and are subject to change before product release.

The following specifications apply for VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range

3 to 252. All limits are at TA = 25°C, unless otherwise specified.

MIN(1)

TYP(1)

MAX(1)

UNIT

fSCLK

SCLK frequency

TA = 25°C

40

MHz

TMIN ≤ TA ≤ TMAX

30

ts

Output voltage settling time(2)

40h to C0h code change

RL = 2 kΩ, CL = 200 pF

TA = 25°C

3

µs

TMIN ≤ TA ≤ TMAX

4.5

SR

Output slew rate

1

V/µs

Glitch impulse

Code change from 80h to 7Fh

12

nV-sec

Digital feedthrough

0.5

nV-sec

Digital crosstalk

1

nV-sec

DAC-to-DAC crosstalk

3

nV-sec

Multiplying bandwidth

VREFIN = 2.5 V ± 0.1 Vpp

160

kHz

Total harmonic distortion

VREFIN = 2.5 V ± 0.1 Vpp

input frequency = 10 kHz

70

dB

tWU

Wake-up time

VA = 3 V

6

µsec

VA = 5 V

39

µsec

1/fSCLK

SCLK cycle time

TA = 25°C

25

ns

TMIN ≤ TA ≤ TMAX

33

tCH

SCLK high time

TA = 25°C

7

ns

TMIN ≤ TA ≤ TMAX

10

tCL

SCLK low Time

TA = 25°C

7

ns

TMIN ≤ TA ≤ TMAX

10

tSS

SYNC set-up time prior to SCLK

falling edge

TA = 25°C

4

ns

TMIN ≤ TA ≤ TMAX

10

tDS

Data set-up time prior to SCLK falling

edge

TA = 25°C

1.5

ns

TMIN ≤ TA ≤ TMAX

3.5

tDH

Data hold time after SCLK falling

edge

TA = 25°C

1.5

ns

TMIN ≤ TA ≤ TMAX

3.5

tCFSR

SCLK fall prior to rise of SYNC

TA = 25°C

0

ns

TMIN ≤ TA ≤ TMAX

3

tSYNC

SYNC high time

TA = 25°C

6

ns

TMIN ≤ TA ≤ TMAX

10