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LP3905 Datasheet(PDF) 3 Page - Texas Instruments |
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LP3905 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 23 page ![]() LP3905 www.ti.com SNVS374D – JUNE 2006 – REVISED MAY 2013 PIN DESCRIPTIONS Pin No. Name Description 1 EN2 Enable Pin for Buck2 2 TGND Ground Pin 3 LDO2 LDO2 Output Pin 4 VIN2 Input Power Terminal to LDO1 and 2 5 LDO1 LDO1 Output Pin 6 GND LDO1 and 2 Ground Pin 7 EN1 Enable Pin for Buck1 and LDO1 and 2 8 FB1 Buck1 Feedback Pin 9 GND_B1 Buck1 Ground Pin 10 SW1 Buck1 Switch Pin 11 VIN1 Input Power Terminal to Buck1 and 2 12 SW2 Buck2 Switch Pin 13 GND_B2 Buck2 Ground Pin 14 FB2 Buck2 Feedback Pin DAP SGND Die Attach Pad (DAP) These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LP3905 |
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