TAS3103ADBT datasheet(53/154 Pages) TI2

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2−20

be included in the data written. There cannot be a separate write transaction to supply the subaddress, as was

required for read transactions. If a subaddress assignment only write transaction is followed by a second write

transaction supplying the data, erroneous behavior results. The first byte in the second write transaction is interpreted

by the TAS3103A as another subaddress replacing the one previously written.

Start

(By Master)

TAS3103A

Address

Acknowledge

(By TAS3103A)

7-Bit Slave

Address

(By Master)

Write

(By Master)

ACK

Subaddress

TAS3103A

Subaddress

(By Master)

Acknowledge

(By TAS3103A)

ACK

Stop

(By Master)

Start

(By Master)

TAS3103A

Address

Acknowledge

(By TAS3103A)

7-Bit Slave

Address

(By Master)

Read

(By Master)

ACK

Data

(By TAS3103A)

ACK

Data

(By TAS3103A)

Acknowledge

(By Master)

ACK

Acknowledge

(By Master)

Stop

(By Master)

NAK

No Acknowledge

(By Master)

Start

(By Master)

TAS3103A

Address

Acknowledge

(By TAS3103A)

7-Bit Slave

Address

(By Master)

Write

(By Master)

ACK

Data

(By Master)

ACK

Data

(By Master)

ACK

Stop

(By Master)

ACK

Subaddress

TAS3103A

Subaddress

(By Master)

Acknowledge

(By TAS3103A)

ACK

Acknowledge

(By TAS3103A)

Acknowledge

(By TAS3103A)

Acknowledge

(By TAS3103A)

I2C Write Transaction

I2C Read Transaction

Figure 2−17. I2C Subaddress Access Protocol

2.3.2.1 I2C Master Mode Operation

The TAS3103A uses the master mode to download an operational configuration. The I2C in master mode is only used

to download initialization parameters from EEPROM following reset or power down. The configuration downloaded

must contain data for all 256 subaddresses, with spacer data supplied for those subaddresses that are GPIO

subaddresses, read-only subaddresses, factory-test subaddresses, or unused (reserved) subaddresses. The spacer

data must always be assigned the value zero. Table 2−4 organizes the 256 subaddresses (and their corresponding

EEPROM addresses) into sequential blocks, with each block containing either valid data or spacer data.

Table 2−4 also illustrates that the subaddresses and their corresponding EEPROM memory addresses do not directly

correlate. This is because many subaddresses are assigned more than one 32-bit word. For example, there is a

unique subaddress for each biquad filter in the TAS3103A, but each subaddress is assigned five 32-bit

coefficients—resulting in 20 bytes of memory being assigned to each biquad subaddress.

The TAS3103A, in the I2C master mode, can execute a complete download without requiring any wait states. After

the TAS3103A has downloaded all 2367 bytes of coefficient and spacer data, the I2C bus is disabled and cannot be

used to update coefficient values or retrieve status or spectrum/VU meter data. Volume control is available in the

master mode via the four GPIO pins.

In I2C master mode, the watchdog timer must not be enabled.

When programming the EEPROM, make sure that the starting I2C check word (subaddress 0x00) and ending I2C

check word (subaddress 0xFC) are identical.

TAS3103ADBT Datasheet(PDF) 53 Page - Texas Instruments

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