VDD

SENSE

OUT

VIT+

V HYS

t pd(LH)

t pd(LH)

t pd(HL)

VIT±

t

d(start)

V(POR)

5

TLV6713

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SBVS331B – JANUARY 2018 – REVISED JULY 2018

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(1)

The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. If less than V(POR), the output is undetermined.

(2)

When VDD falls below UVLO, OUT is driven low. The output cannot be determined if less than V(POR).

7.5 Electrical Characteristics

Over the operating temperature range of TJ = –40°C to +125°C, 1.8 V ≤ VDD < 36 V, and pullup resistor RP = 100 kΩ (unless

otherwise noted). Typical values are at TJ = 25°C and VDD = 12 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V(POR)

Power-on reset voltage(1)

VOL ≤ 0.2 V

0.8

V

VIT–

SENSE pin negative input threshold voltage

VDD = 1.8 V to 36 V

397

400

403

mV

VIT+

SENSE pin positive input threshold voltage

VDD = 1.8 V to 36 V

400

405.5

413

mV

VHYS

SENSE pin hysteresis voltage

(HYS = VIT+ – VIT–)

2

5.5

12

mV

VOL

Low-level output voltage

VDD = 1.8 V, IOUT = 3 mA

130

250

mV

VDD = 5 V, IOUT = 5 mA

150

250

IIN

Input current (at SENSE pin)

VDD = 1.8 V and 36 V, VSENSE = 6.5 V

–25

+1

+25

nA

VDD = 1.8 V and 36 V, VSENSE = 0.1 V

–15

+1

+15

ID(leak)

Open-drain leakage current

VDD = 1.8 V and 36 V, VOUT = 25 V

10

300

nA

IDD

Supply current

VDD = 1.8 V – 36 V

8

11

µA

UVLO

Undervoltage lockout(2)

VDD falling

1.3

1.5

1.7

V

(1)

High-to-low and low-to-high refers to the transition at the input pin (SENSE).

(2)

During power on, VDD must exceed 1.8 V for at least 150 µs (typical) before the output state reflects the input condition.

7.6 Timing Requirements

MIN

NOM

MAX

UNIT

tpd(HL)

High-to-low propagation delay(1)

VDD = 24 V, ±10-mV input overdrive,

RL = 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV

9.9

µs

tpd(LH)

Low-to-high propagation delay(1)

VDD = 24 V, ±10-mV input overdrive,

RL = 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV

28.1

µs

td(start)

(2)

Startup delay

VDD = 5 V

155

µs

tr

Output rise time

VDD = 12 V, 10-mV input overdrive,

RL = 100 kΩ, CL = 10 pF, VO = (0.1 to 0.9) × VDD

2.7

µs

tf

Output fall time

VDD = 12 V, 10-mV input overdrive,

RL = 100 kΩ, CL = 10 pF, VO = (0.9 to 0.1) × VDD

0.12

µs

Figure 1. Timing Diagram