9

TLV6713

www.ti.com

SBVS331B – JANUARY 2018 – REVISED JULY 2018

Product Folder Links: TLV6713

Submit Documentation Feedback

Copyright © 2018, Texas Instruments Incorporated

8.3 Feature Description

8.3.1 Input Pin (SENSE)

The TLV6713 combines a comparator with a precision reference voltage. The comparator has one external input

and one internal input connected to the internal reference. The falling threshold on SENSE is designed and

trimmed to be equal to the reference voltage (400 mV). This configuration optimizes the device accuracy. The

comparator also has built-in hysteresis that proves immunity to noise and ensures stable operation.

The comparator input swings from ground to 1.7 V (7 V absolute maximum), regardless of the device supply

voltage used. Although not required in most cases, it is good analog design practice to place a 1-nF to 10-nF

bypass capacitor at the comparator input for noisy applications to reduce sensitivity to transient voltage changes

on the monitored signal.

For the comparator, the output (OUT) is driven to logic low when the input SENSE voltage drops below VIT–.

When the voltage exceeds VIT+, OUT goes to a high-impedance state; see Figure 1.

8.3.2 Output Pin (OUT)

In a typical TLV6713 application, the output is connected to a GPIO input of the processor (such as a digital

signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or application-

specific integrated circuit [ASIC]).

The TLV6713 provides an open-drain output (OUT) rated to 25 V, independant of supply voltage, and can sink

up to 40 mA.. A pullup resistor is required to hold the line high when the output goes to a high-impedance state.

Connect this pullup resistor to a voltage rail that meets the logic requirements of the downstream device. To

ensure the proper voltage level, give some consideration when choosing the pullup resistor value. The pullup

resistor value is determined by VOL, output capacitive loading, and the open-drain leakage current (ID(leak)). These

values are specified in the Electrical Characteristics table.

Table 2 and Input Pin (SENSE) describe how the output is asserted or high impedance. See Figure 1 for a timing

diagram that describes the relationship between threshold voltage and the respective output.

8.4 Device Functional Modes

8.4.1 Normal Operation (VDD > UVLO)

When the voltage on VDD is greater than 1.8 V for at least 155 µs, the OUT signal corresponds to the voltage on

SENSE, as listed in Table 2.

8.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)

When the voltage on VDD is less than the device UVLO voltage, and greater than the power-on reset voltage,

V(POR), the OUT signal is asserted regardless of the voltage on SENSE.

8.4.3 Power On Reset (VDD < V(POR))

When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND

(V(POR)), OUT is in a high-impedance state.