HI

pullup

D(leak

pullu

UT

)

p

O

V

V

RP

I

V

I

d

d

MON(UV)

IT-

R1

V

= 1 +

V

R2

·

§

u

¨

¸

©

¹

12

TLV6713

SBVS331B – JANUARY 2018 – REVISED JULY 2018

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Copyright © 2018, Texas Instruments Incorporated

Typical Application (continued)

9.2.1 Design Requirements

This typical voltage detector application is designed to meet the parameters listed in Table 3:

Table 3. Design Parameters

PARAMETER

DESIGN REQUIREMENT

DESIGN RESULT

Monitored voltage

24-V nominal, falling (VMON(UV))

threshold

10% nominal (21.6 V)

VMON(UV) = 21.8 V ±2.7%

Output logic voltage

3.3-V CMOS

3.3-V CMOS

Maximum current consumption

30 µA

24 µA

9.2.2 Detailed Design Procedure

9.2.2.1 Resistor Divider Selection

The resistor divider values and target threshold voltage can be calculated by using Equation 1 to determine

VMON(UV).

where

•

R1 and R2 are the resistor values for the resistor divider on the SENSE pin

•

VMON(UV) is the target voltage at which an undervoltage condition is detected

(1)

Choose an RTOTAL ( = R1 + R2) so that the current through the divider is approximately 100 times higher than the

input current at the SENSE pin. Use resistors with high values to minimize current consumption (as a result of

low input bias current) without adding significant error to the resistive divider. For details on sizing input resistors,

refer to Optimizing Resistor Dividers at a Comparator Input, available for download from www.ti.com.

9.2.2.2 Pullup Resistor Selection

To ensure the proper logic-high voltage level (VHI), select a pullup resistor value where the pullup voltage divided

by the pullup resistor value does not exceed the sink-current capability of the device. Confirm this voltage level

by verifying that the pullup voltage minus the open-drain leakage current (ID(leak) ) multiplied by the resistor is

greater than the desired VHI. These values are specified in the Electrical Characteristics.

Use Equation 2 to calculate the value of the pullup resistor.

(2)

9.2.2.3 Input Supply Capacitor

Although an input capacitor is not required for stability, for good analog design practice, connect a 0.1-μF low

equivalent series resistance (ESR) capacitor across the VDD and GND pins. A higher-value capacitor may be

necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power

source.