1.5A, 40V, MAXPower Step-Down

DC-DC Converters

12

______________________________________________________________________________________

equal to 20% and 80%, respectively.

peak inductor current (see the Input Capacitors Selection

The allowable deviation of the output voltage during

fast load transients also determines the output capaci-

tance, its ESR, and its equivalent series inductance

(ESL). The output capacitor supplies the load current

during a load step until the controller responds with a

depends on the closed-loop bandwidth of the converter

(see the Compensation Design section). The resistive

drop across the output capacitor’s ESR, the drop

across the capacitor’s ESL (

discharge causes a voltage droop during the load-

step. Use a combination of low-ESR tantalum/aluminum

electrolyte and ceramic capacitors for better transient

load and voltage ripple performance. Nonleaded

capacitors and capacitors in parallel help reduce the

ESL. Keep the maximum output voltage deviation

below the tolerable limits of the electronics being pow-

ered. Use the following equations to calculate the

required ESR, ESL, and capacitance value during a

load step:

controller.

Compensation Design

The MAX5082/MAX5083 use a voltage-mode control

scheme that regulates the output voltage by comparing

the error amplifier output (COMP) with an internal ramp

to produce the required duty cycle. The output lowpass

LC filter creates a double pole at the resonant frequen-

cy, which has a gain drop of -40dB/decade. The error

amplifier must compensate for this gain drop and phase

shift to achieve a stable closed-loop system.

The basic regulator loop consists of a power modulator,

an output feedback divider, and a voltage-error amplifi-

er. The power modulator has a DC gain set by

the output inductance (L), the output capacitance

equivalent series resistance (ESR). The power modula-

tor incorporates a voltage feed-forward feature, which

automatically adjusts for variations in the input voltage

resulting in a DC gain of 10. The following equations

define the power modulator:

The switching frequency is internally set at 250kHz or

can vary from 150kHz to 350kHz when driven with an

which is the frequency when the closed-loop gain is

equal to unity, should be set at 15kHz or below therefore:

≤ 15kHz

The error amplifier must provide a gain and phase

bump to compensate for the rapid gain and phase loss

from the LC double pole. This is accomplished by utiliz-

ing a type 3 compensator that introduces two zeroes

and 3 poles into the control loop. The error amplifier

The two zeros are at:

and the higher frequency poles are at:

Figure 3 shows the error amplifier feedback as well as

its gain response for circuits that use low-ESR output

pensate for the gain and phase loss due to the double

pole. Choose the inductor (L) and output capacitor

Capacitor Selection section.

f

RC

and f

R

CC

CC

PP

23

1

26

6

1

25

78

78

=

××

=

××

×

+

⎛

⎝⎜

⎞

⎠⎟

π

π

f

1

f

1

Z1

Z2

=

××

=

×+×

25

7

2

6

3

6

ππ

RC

and

RR

C

()

G

V

V

f

LC

f

C

ESR

MOD DC

IN

RAMP

LC

OUT

ZESR

OUT

=

×

=

××

10

1

2

1

2

π

π

E

V

C

V

E

V

ESR

STEP

OUT

STEP

RESPONSE

Q

ESL

STEP

STEP

SR

I

It

SL

t

I

=

=

=

×

×

∆

∆

∆