AMC1035 datasheet(7/36 Pages) TI2

7 / 36 page

CLKIN

DOUT

Bitstream not valid (analog settling)

VDD

...

Valid bitstream

tASTART

CLKIN

DOUT

(MCE = 0)

tCLKIN

tHIGH

tLOW

tD1

tH1

tr / tf

DOUT

(MCE = 1)

tD2

tr / tf

tD3

tH2

tH3

AMC1035

www.ti.com

SBAS837B – AUGUST 2018 – REVISED APRIL 2020

Product Folder Links: AMC1035

Submit Documentation Feedback

(1)

The duty cycle of DOUT equals the clock duty cycle of the applied CLKIN signal.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fCLKIN

CLKIN clock frequency

MCE = 0

MHz

MCE = 1

DutyCycle

CLKIN clock duty cycle(1)

40%

50%

60%

tH1

DOUT hold time after rising edge of CLKIN

MCE = 0, CLOAD = 15 pF

tH2

DOUT hold time after rising edge of CLKIN

MCE = 1, CLOAD = 15 pF

tH3

DOUT hold time after falling edge of CLKIN

MCE = 1, CLOAD = 15 pF

tD1

Rising edge of CLKIN to DOUT valid delay

MCE = 0, CLOAD = 15 pF

tD2

Rising edge of CLKIN to DOUT valid delay

MCE = 1, CLOAD = 15 pF

tD3

Falling edge of CLKIN to DOUT valid delay

MCE = 1, CLOAD = 15 pF

DOUT rise time

10% to 90%, 3.0 V

≤ VDD ≤ 3.6 V,

CLOAD = 15 pF

2.5

10% to 90%, 4.5 V

≤ VDD ≤ 5.5 V,

CLOAD = 15 pF

1.5

3.5

DOUT fall time

90% to 10%, 3.0 V

≤ VDD ≤ 3.6 V,

CLOAD = 15 pF

2.5

5.8

90% to 10%, 4.5 V

≤ VDD ≤ 5.5 V,

CLOAD = 15 pF

1.8

4.4

tASTART

Analog startup time

VDD step to 3.0 V, 0.1% settling,

CLKIN applied

0.25

Figure 1. Digital Interface Timing

Figure 2. Device Startup Timing

AMC1035 Datasheet(PDF) 7 Page - Texas Instruments

AMC1035 Datasheet(HTML) 7 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL