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ADS1148IPWR Datasheet(PDF) 39 Page - Texas Instruments

Part # ADS1148IPWR
Description  ADS114x 16-Bit, 2-kSPS, Analog-to-Digital Converters With Programmable Gain Amplifier (PGA) for Sensor Measurement
PDF  100 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

ADS1148IPWR Datasheet(HTML) 39 Page - Texas Instruments

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DIN
DOUT
DRDY
RDATAC
SCLK
16Bits
1
8
1
16
NOP
0001010X
SCLK
DOUT
DIN
DRDY
NOP
NOP
NOP
RDATA
NOP
NOP
1
D[15]
D[6]
D[1]
D[1]
D[0]
D[9]
D[8]
D[7]
D[14]
D[15] D[14]
2
1
2
9
10
7
8
15
16
15
16
D[0]
SCLK
DIN
DOUT
DRDY
MSB
0001001X
LSB
1
8
1
16
NOP
NOP
RDATA
39
ADS1146, ADS1147, ADS1148
www.ti.com
SBAS453G – JULY 2009 – REVISED AUGUST 2016
Product Folder Links: ADS1146 ADS1147 ADS1148
Submit Documentation Feedback
Copyright © 2009–2016, Texas Instruments Incorporated
9.5.3.5 RDATA (0001 001x)
The RDATA command loads the most recent conversion result into the output register. After issuing this
command, the conversion result is read out by sending 16 SCLKs, as shown in Figure 49. This command also
works in RDATAC mode.
Figure 49. Figure Read Data Once
When performing multiple reads of the conversion result, the RDATA command can be sent when the last eight
bits of the conversion result are being shifted out during the course of the first read operation by taking
advantage of the duplex communication nature of the serial interface, as shown in Figure 50.
Figure 50. Using RDATA in Full-Duplex Mode
9.5.3.6 RDATAC (0001 010x)
The RDATAC command enables read data continuous mode. This is the default mode after a power up or reset.
In read data continuous mode, new conversion results are automatically loaded onto DOUT. The conversion
result can be received from the device after the DRDY signal goes low by sending 16 SCLKs. It is not necessary
to read back all the bits, as long as the number of bits read out is a multiple of eight. The RDATAC command
must be issued after DRDY goes low, and the command takes effect on the next DRDY as shown in Figure 51.
Be sure to complete data retrieval (conversion result or register read-back) before DRDY returns low, or the
resulting data is corrupted. Successful register read operations in RDATAC mode require the knowledge of when
the next DRDY falling edge occurs.
Figure 51. Read Data Continuously



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