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ADS5231

SBAS295A – JULY 2004 – REVISED JANUARY 2007

ELECTRICAL CHARACTERISTICS (continued)

T

MIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 40MSPS, 50% clock duty cycle,

AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, I

SET = 56.2kΩ, and internal voltage reference, unless

otherwise noted.

ADS5231

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

ANALOG INPUT

Differential Input Capacitance

3

pF

Analog Input Common-Mode Range

VCM ± 0.05

V

Differential Input Voltage Range

Internal Reference

2.02

VPP

External Reference

2.02

× (VREF

T – VREFB)

VPP

Voltage Overload Recovery Time(8)

3

CLK Cycles

–3dBFS Input, 25

Ω Series

Input Bandwidth

300

MHz

Resistance

DIGITAL DATA INPUTS

Logic Family

+3V CMOS Compatible

VIH High-Level Input Voltage

VIN = 3.3V

2.2

V

VIL Low-Level Input Voltage

VIN = 3.3V

0.6

V

CIN Input Capacitance

3

pF

DIGITAL OUTPUTS

Data Format

Straight Offset Binary(9)

Logic Family

CMOS

Logic Coding

Straight Offset Binary or BTC

Low Output Voltage (IOL = 50µA)

+0.4

V

High Output Voltage (IOH = 50µA)

+2.4

V

3-State Enable Time

2

Clocks

3-State Disable Time

2

Clocks

Output Capacitance

3

pF

SERIAL INTERFACE

SCLK Serial Clock Input Frequency

20

MHz

CONVERSION CHARACTERISTICS

Sample Rate

20

40

MSPS

Data Latency

6

CLK Cycles

(8)

A differential ON/OFF pulse is applied to the ADC input. The differential amplitude of the pulse in its ON (high) state is twice the

full-scale range of the ADC, while the differential amplitude of the pulse in its OFF (low) state is zero. The overload recovery time of the

ADC is measured as the time required by the ADC output code to settle within 1% of full-scale, as measured from its mid-code value

when the pulse is switched from ON (high) to OFF (low).

(9)

Option for Binary Two’s Complement Output.

5

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