ADS54J69IRMP datasheet(21/83 Pages) TI2

21 / 83 page

Input Frequency (MHz)

100

150

200

250

-120

-100

-80

-60

-40

-20

D047

Frequency of Input Common-Mode Signal (MHz)

100

150

200

250

300

-60

-55

-50

-45

-40

-35

-30

-25

-20

D048

Input Frequency (MHz)

100

150

200

250

-120

-100

-80

-60

-40

-20

D045

Frequency of Signal on Supply (MHz)

100

150

200

250

300

-70

-60

-50

-40

-30

-20

-10

D046

PSRR with 50-mVPP Signal on AVDD

PSRR with 50-mVPP Signal on AVDD3V

Input Clock Duty Cycle (%)

100

D043

SNR

SFDR

Input Clock Duty Cycle (%)

D044

SNR

SFDR

ADS54J69

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SBAS713C – MAY 2015 – REVISED JANUARY 2017

Product Folder Links: ADS54J69

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Typical Characteristics (continued)

typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, device clock frequency =

1 GSPS, output sampling rate = 500 MSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD =

1.15 V, and –1-dBFS differential input (unless otherwise noted)

fIN = 185 MHz

Figure 45. Performance vs Input Clock Duty Cycle

fIN = 300 MHz

Figure 46. Performance vs Input Clock Duty Cycle

AIN = –1 dBFS, SFDR = 84 dBc, SINAD = 70 dBFS,

fPSRR = 5 MHz, APSRR = 50 mVPP, fIN = 185 MHz,

amplitude: fIN – fPSRR = 85 dBc, fIN + fPSRR = 84 dBc

Figure 47. Power-Supply Rejection Ratio FFT for

AVDD Supply

fIN = 185 MHz

Figure 48. Power-Supply Rejection Ratio vs

Noise Signal Frequency

AIN = –1 dBFS, SFDR = 78 dBc, SINAD = 71 dBFS,

fCMRR = 5 MHz, ACMRR = 50 mVPP, fIN = 185 MHz,

amplitude: fIN – fCMRR = 79 dBc, fIN + fCMRR = 80 dBc

Figure 49. Common-Mode Rejection Ratio FFT

fIN = 185 MHz

Figure 50. Common-Mode Rejection Ratio vs

Common-Mode Signal Frequency

ADS54J69IRMP Datasheet(PDF) 21 Page - Texas Instruments

ADS54J69IRMP Datasheet(HTML) 21 Page - Texas Instruments

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