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ADS54J69IRMP Datasheet(PDF) 29 Page - Texas Instruments

Part # ADS54J69IRMP
Description  ADS54J69 Dual-Channel, 16-Bit, 500-MSPS, Analog-to-Digital Converter
PDF  83 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

ADS54J69IRMP Datasheet(HTML) 29 Page - Texas Instruments

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ADS54J69
www.ti.com
SBAS713C – MAY 2015 – REVISED JANUARY 2017
Product Folder Links: ADS54J69
Submit Documentation Feedback
Copyright © 2015–2017, Texas Instruments Incorporated
8.3.5 Power-Down Mode
The ADS54J69 provides a highly-configurable power-down mode. Power-down can be enabled by using the
PDN pin or via SPI register writes.
A power-down mask can be configured that allows a trade-off between wake-up time and power consumption in
power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2, as shown in
Table 4. See the master page registers in Table 10 for further details.
Table 4. Register Address for Power-Down Modes
REGISTER
ADDRESS
COMMENT
REGISTER DATA
A[7:0] (Hex)
7
6
5
4
3
2
1
0
MASTER PAGE (80h)
20
MASK 1
PDN ADC CHA
PDN ADC CHB
21
PDN BUFFER CHB
PDN BUFFER CHA
0
0
0
0
23
MASK 2
PDN ADC CHA
PDN ADC CHB
24
PDN BUFFER CHB
PDN BUFFER CHA
0
0
0
0
26
CONFIG
GLOBAL
PDN
OVERRIDE
PDN PIN
PDN MASK
SEL
0
0
0
0
0
53
0
MASK
SYSREF
0
0
0
0
0
0
55
0
0
0
PDN MASK
0
0
0
0
To save power, the device can be put in complete power-down by using the GLOBAL PDN register bit. However,
when the JESD link is required to be active during power-down, the ADC and analog buffer can be selectively
powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN MASK
register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. Table 5 shows
power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF CHx
register bits.
Table 5. Power Consumption in Different Power-Down Settings
REGISTER BIT
COMMENT
IAVDD3V
(mA)
IAVDD
(mA)
IDVDD
(mA)
IIOVDD
(mA)
TOTAL
POWER
(W)
Default
After reset, with a full-scale input signal to both
channels
346
354
188
512
2.66
GBL PDN = 1
The device is in a complete power-down state
3
6
21
127
0.2
GBL PDN = 0,
PDN ADC CHx = 1
(x = A or B)
The ADC of one channel is powered down
284
221
130
461
2.05
GBL PDN = 0,
PDN BUFF CHx = 1
(x = A or B)
The input buffer of one channel is powered down
270
352
188
516
2.43
GBL PDN = 0,
PDN ADC CHx = 1,
PDN BUFF CHx = 1
(x = A or B)
The ADC and input buffer of one channel are
powered down
206
220
129
465
1.82
GBL PDN = 0,
PDN ADC CHx = 1,
PDN BUFF CHx = 1
(x = A and B)
The ADC and input buffer of both channels are
powered down
64
84
67
389
0.93



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