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ADS7040 Datasheet(PDF) 28 Page - Texas Instruments |
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ADS7040 Datasheet(HTML) 28 Page - Texas Instruments |
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28 / 43 page ![]() + ± AVDD AINP AINM GND AVDD Device ROUT CFLT Sensor ADS7040 SBAS676C – NOVEMBER 2014 – REVISED DECEMBER 2015 www.ti.com 9.2.3 8-Bit, 10-kSPS DAQ Circuit Optimized for DC Sensor Measurements Figure 45. Interfacing the Device Directly with Sensors In applications where the input is very slow moving and the overall system ENOB is not a critical parameter, a DAQ circuit can be designed without the input driver for the ADC . This type of a use case is of particular interest for applications in which the primary goal is to achieve the absolute lowest power possible. Typical applications that fall into this category are low-power sensor applications (such as temperature, pressure, humidity, gas, and chemical). 9.2.3.1 Design Requirements For this design example, use the parameters listed in Table 4 as the input parameters. Table 4. Design Parameters DESIGN PARAMETER GOAL VALUE Throughput 10 kSPS SNR at 100 Hz 48.5 dB THD at 100 Hz 65dB SINAD at 100 Hz 48 dB ENOB 7.5 Power 10 µW 9.2.3.2 Detailed Design Procedure The ADS7040 can be directly interfaced with sensors at lower throughputs without the need of an amplifier buffer. The analog input source drive must be capable of driving the switched capacitor load of a SAR ADC and settling the analog input signal within the acquisition time of the SAR ADC. However, the output impedance of the sensor must be taken into account when interfacing a SAR ADC directly with sensors. Drive the analog input of the SAR ADC with a low impedance source. The input signal requires more acquisition time to settle to the desired accuracy because of the higher output impedance of the sensor. The simplified circuit for a sensor as a voltage source with output impedance (ROUT) is shown in Figure 45. The acquisition time of a SAR ADC (such as the ADS7040) can be increased by reducing throughput in the following ways: 1. Reducing the SCLK frequency to reduce the throughput, or 2. Keeping the SCLK fixed at the highest permissible value (that is, 12 MHz for the device) and increasing the CS high time. 28 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: ADS7040 |
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