CS

SCLK

SDI

Bit 1

Bit 0

t

8

t

4

t

1

t

3

t

2

Bit 23

t

f

t

r

t

5

t

6

t

7

t

10

CS

SCLK

SDI

Bit 23

Bit 0

SDO

Bit 23

Bit 23

Bit 1

Bit 1

Bit 0

Bit 0

t9

Read Command

Any Command

Data read from the register selected in previous operation

t

f

t8

t4

t7

t1

t2

t3

tr

t5

t6

AMC7891

www.ti.com

SBAS518A

– AUGUST 2011 – REVISED DECEMBER 2011

TIMING SPECIFICATIONS

(1) (2)

AVDD = 4.75 to 5.5 V, GPIOVDD = 1.8 to 5.5 V, SPIVDD = 1.8 to 5.5 V, AGND = DGND = 0 V, External ADC reference = AVDD,

TA = –40°C to 105°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SPIVDD = 5.5 V

30

MHz

fSCLK

SCLK frequency

SPIVDD = 2.7 V

15

MHz

SPIVDD = 1.8 V

10

MHz

tR

Input rise time

10% to 90% of SPIVDD

2

ns

tF

Input fall time

10% to 90% of SPIVDD

2

ns

SPIVDD = 5.5 V

33

ns

t1

SCLK cycle time

SPIVDD = 2.7 V

66

ns

SPIVDD = 1.8 V

100

ns

SPIVDD = 5.5 V

13

ns

t2

SCLK high time

SPIVDD = 2.7 V

30

ns

SPIVDD = 1.8 V

50

ns

SPIVDD = 5.5 V

13

ns

t3

SCLK low time

SPIVDD = 2.7 V

26

ns

SPIVDD = 1.8 V

40

ns

t4

Frame start time

CS falling edge to SCLK rising edge

5

ns

t5

SDI setup time

SDI valid to falling edge of SCLK

4

ns

t6

SDI hold time

SDI valid after falling edge of SCLK

12

ns

t7

Frame stop time

SCLK falling edge to CS rising edge

15

ns

t8

CS high time

50

ns

SPIVDD = 5.5 V, CL = 10 pF, 1 ns ≤ tR,F(SDO) ≤ 4 ns

5

16

ns

t9

SDO delay

SPIVDD = 2.7 V, CL = 10 pF, 1 ns ≤ tR,F(SDO) ≤ 5 ns

6

22

ns

SPIVDD = 1.8 V, CL = 10 pF, 2 ns ≤ tR,F(SDO) ≤ 8 ns

8

39

ns

t10

Wait time

CS rising edge to next SCLK rising edge

5

ns

(1)

Specified by design. Not tested during production.

(2)

Digital inputs and outputs timed from a voltage level of SPIVDD/2.

TIMING INFORMATION

Figure 1. Serial Interface Write Timing Diagram

Figure 2. Serial Interface Read Timing Diagram

Copyright

© 2011, Texas Instruments Incorporated

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