STA529Q datasheet(34/57 Pages) STMICROELECTRONICS

34 / 57 page

I2C interface

STA529

34/57

Doc ID 13095 Rev 3

I2C interface

10.1

Data transition and change

Data changes on the SDA line must only occur when the SCL clock is low. SDA transition

while the clock is high is used to identify a start or stop condition.

10.2

Start condition

A start condition is identified by a high to low transition of the data bus SDA signal while the

clock signal SCL is stable in the high state. A start condition must precede any command for

data transfer.

10.3

Stop condition

A stop condition is identified by low to high transition of the data bus SDA signal while the

clock signal SCL is stable in the high state. A stop condition terminates communication

between the STA529 and the master bus.

10.4

Data input

During data input, the STA529 samples the SDA signal on the rising edge of clock SCL. For

correct device operation the SDA signal must be stable during the rising edge of the clock

and the data can change only when the SCL line is low.

10.5

Device addressing

To start communication between the master and the STA529, the master must initiate with a

start condition. Following this, the master sends 8 bits (MSB first) on the SDA line

corresponding to the device select address and read or write mode.

The 7 most significant bits are the device address identifiers, corresponding to the I2C bus

definition. In the STA529, the I2C interface has the device address 0x34.

The 8th bit (LSB) identifies the read or write operation (R/W). It is set to 1 in read mode and

0 in write mode.

After the start condition, the STA529 waits for its device address on SDA. When a match is

found, it acknowledges the identification on SDA during the 9th bit time. The byte following

the device identification byte is the internal space address.

STA529Q Datasheet(PDF) 34 Page - STMicroelectronics