STA529Q datasheet(35/57 Pages) STMICROELECTRONICS

35 / 57 page

STA529

I2C interface

Doc ID 13095 Rev 3

35/57

10.6

Write operation

Following the start condition the master sends a device select code with the R/W bit set to 0.

The STA529 acknowledges this and then writes to the byte of the internal address. After

receiving the internal byte address, the STA529 responds with an acknowledgement.

10.6.1

Byte write

In the byte-write mode the master sends one data byte. This is acknowledged by the

STA529. The master then terminates the transfer by generating a stop condition.

10.6.2

Multi-byte write

The multi-byte write modes can start from any internal address. The master generates a

stop condition which terminates the transfer.

10.7

Read operation

10.7.1

Current address byte read

Following the start condition the master sends a device select code with bit R/W set to 1.

The STA529 acknowledges this and then responds by sending one byte of data. The master

then terminates the transfer by generating a stop condition.

10.7.2

Current address multi-byte read

The multi-byte read modes can start from any internal address. Sequential data bytes are

read from sequential addresses within the STA529. The master acknowledges each data

byte read and then generates a stop condition terminating the transfer.

10.7.3

Random address byte read

Following the start condition the master sends a device select code with bit R/W set to 0.

The STA529 acknowledges this and then the master writes the internal address byte. After

receiving the internal byte address, the STA529 again responds with an acknowledgement.

The master then initiates another start condition and sends the device select code with bit

R/W set to 1. The STA529 acknowledges this and then responds by sending one byte of

data. The master then terminates the transfer by generating a stop condition.

STA529Q Datasheet(PDF) 35 Page - STMicroelectronics