3 Pin Configuration and Functions

Figure 3-1. CD54AC74 F Package, 14-Pin CDIP; CD74AC74 E or M Package, 14-Pin PDIP or SOIC (Top

View)

Pin Functions

PIN

I/O

DESCRIPTION

NAME

NO.

1 CLR

1

Input

Channel 1, Clear Input, Active Low

1D

2

Input

Channel 1, Data Input

1CLK

3

Input

Channel 1, Positive edge triggered clock input

1 PRE

4

Input

Channel 1, Preset Input, Active Low

1Q

5

Output

Channel 1, Output

1 Q

6

Output

Channel 1, Inverted Output

GND

7

—

Ground

2 Q

8

Output

Channel 2, Inverted Output

2Q

9

Output

Channel 2, Output

2 PRE

10

Input

Channel 2, Preset Input, Active Low

2CLK

11

Input

Channel 2, Positive edge triggered clock input

2D

12

Input

Channel 2, Data Input

2 CLR

13

Input

Channel 2, Clear Input, Active Low

VCC

14

—

Positive Supply

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CD54AC74, CD74AC74

SCHS231E – NOVEMBER 1998 – REVISED AUGUST 2024

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Product Folder Links: CD54AC74 CD74AC74