6 Detailed Description

6.1 Overview

The ’AC74 dual positive-edge-triggered devices are D-type flip-flops.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of

the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time

requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,

data at the D input can be changed without affecting the levels at the outputs.

6.2 Functional Block Diagram

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Figure 6-1.

6.3 Device Functional Modes

Table 6-1. Function Table (Each Flip-flop)

INPUTS

OUTPUTS

PRE

CLR

CLK

D

Q

Q

L

H

X

X

H

L

H

L

X

X

L

H

L

L

X

X

H

(1)

H

(1)

H

H

↑

H

H

L

H

H

↑

L

L

H

H

H

L

X

Q0

Q 0

(1)

This configuration is nonstable; that is, it does not persist when

PRE or CLR returns to its inactive (high) level.

CD54AC74, CD74AC74

SCHS231E – NOVEMBER 1998 – REVISED AUGUST 2024

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