L9678P datasheet(140/215 Pages) STMICROELECTRONICS

140 / 215 page

Watchdog timer

L9678P, L9678P-S

140/216

DS11626 Rev 9

Figure 37. Watchdog timer refresh diagram

8.2

Watchdog reset assertion timer

Upon a watchdog reset, the watchdog logic will momentarily assert the RESET pin for time

duration twdrst. When the RESET pin has been asserted through the watchdog reset

assertion timer, stored faults are maintained and can be read by the microcontroller via SPI

following the RESET period.

8.3

Watchdog timer disable input (WDT/TM)

This input pin has a passive pull-down and is used to disable the watchdog timer. The state

of this pin can be read by SPI through the WDTDIS_S bit in the GSW register. When

WDT/TM pin is asserted, the watchdog timer is disabled, the timer is reset to its starting

value and no faults are generated.

The WDT/TM input pin must not be biased HIGH (WDT/TM > VWD_OVERRIDE_th) prior to

POR in order to have a proper start-up.

GAPGPS01659

WD1INIT

WD1A1

WD1B1

WD1B2

WD1A2

WD1_ERROR

SPI_WD1_B

SPI_WD1_A

SSM_RESET

TMR1>MIN &

SPI_WD1_A /

TMR1=0

Strobe WD1 refresh OK

TMR1>MIN &

SPI_WD1_B /

TMR1=0

Strobe WD1 refresh OK

TMR1>MAX OR

[TMR1<MIN & SPI_WD1_B]

TMR1>MAX OR

[TMR1<MIN & SPI_WD1_A]

L9678P Datasheet(PDF) 140 Page - STMicroelectronics