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INA828

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SBOS792A – AUGUST 2017 – REVISED JANUARY 2018

Product Folder Links: INA828

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Copyright © 2017–2018, Texas Instruments Incorporated

9 Power Supply Recommendations

The nominal performance of the INA828 is specified with a supply voltage of ±15 V and mid-supply reference

voltage. The device can also be operated using power supplies from ±1.5 V (3 V) to ±18 V (36 V) and non mid-

supply reference voltages with excellent performance. Parameters that can vary significantly with operating

voltage and reference voltage are illustrated in the Typical Characteristics section.

10 Layout

10.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use

good PCB layout practices, including:

•

Care must be taken to assure that both input paths are well-matched for source impedance and capacitance

to avoid converting common-mode signals into differential signals. In addition, parasitic capacitance at the

gain-setting pins can also affect CMRR over frequency. For example, in applications that implement gain

switching using switches or PhotoMOS® relays to change the value of RG, select the component so that the

switch capacitance is as small as possible.

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the device

itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources

local to the analog circuitry.

–

Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If

these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in

parallel with the noisy trace.

•

Place the external components as close to the device as possible. As illustrated in Figure 74, keeping RG

close to the pins minimizes parasitic capacitance.

•

Keep the traces as short as possible.