4

3

2

1

Time (t)

Recessive

Logic H

Dominant

Logic L

Recessive

Logic H

CANH

CANL

Vdiff(D)

Vdiff(R)

Figure 8-1. Bus States (Physical Bit Representation)

RXD

V

CC / 2

CANH

CANL

Figure 8-2. Simplified Recessive Common Mode Bias and Receiver

8.3.2 Digital Inputs and Outputs: TXD (Input) and RXD (Output)

The VCC1 supply for the isolated digital input and output side of the device can be supplied by 1.8-V, 2.5-V, 3.3-V,

and 5-V supplies and therefore the digital inputs and outputs are 1.8-V, 2.5-V, 3.3-V, and 5-V compatible.

8.3.3 Protection Features

8.3.3.1 TXD Dominant Timeout (DTO)

The TXD DTO circuit prevents the transceiver from blocking network communication in the event of a hardware

or software failure where the TXD pin is held dominant longer than the timeout period, tTXD_DTO. The DTO circuit

timer starts on a falling edge on the TXD pin. The DTO circuit disables the CAN bus driver if no rising edge

occurs before the timeout period expires, which frees the bus for communication between other nodes on the

network. The CAN driver is activated again when a recessive signal occurs on the TXD pin, clearing the TXD

DTO condition. The receiver and RXD pin still reflect activity on the CAN bus, and the bus terminals are biased

to the recessive level during a TXD dominant timeout.

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ISO1044

SLLSFB0A – MARCH 2020 – REVISED JULY 2020

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