DDC112 datasheet(12/37 Pages) TI2

12 / 37 page

DDC112

SBAS085B

www.ti.com

CLK = 10MHz

CLK = 15MHz

SYMBOL

DESCRIPTION

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Setup Time for Test Mode Enable

100

Setup Time for Test Mode Disable

100

Hold Time for Test Mode Enable

100

From Rising Edge of TEST to the Edge of CONV

5.4

3.6

µs

while Test Mode Enabled

Rising Edge to Rising Edge of TEST

5.4

3.6

µs

A low-pass filter to reduce noise connects it to an opera-

tional amplifier configured as a buffer. This amplifier should

have a unity-gain bandwidth greater than 4MHz, low noise,

and input/output common-mode ranges that support VREF.

Following the buffer are capacitors placed close to the

DDC112 VREF pin. Even though the circuit in Figure 6 might

appear to be unstable due to the large output capacitors, it

works well for most operational amplifiers. It is NOT recom-

mended that series resistance be placed in the output lead

to improve stability since this can cause droop in VREF which

produces large offsets.

DDC112 Frequency Response

The frequency response of the DDC112 is set by the front end

integrators and is that of a traditional continuous time integra-

tor, as shown in Figure 7. By adjusting TINT, the user can

change the 3dB bandwidth and the location of the notches in

the response. The frequency response of the

∆Σ converter that

follows the front end integrator is of no consequence because

the converter samples a held signal from the integrators. That

is, the input to the

∆Σ converter is always a DC signal. Since

the output of the front end integrators are sampled, aliasing can

occur. Whenever the frequency of the input signal exceeds

one-half of the sampling rate, the signal will

fold back down to

lower frequencies.

Test Mode

When TEST is used, pins IN1 and IN2 are grounded and

packets of approximately 13pC charge are transferred to the

FIGURE 8. Timing Diagram of the Test Mode of the DDC112.

TABLE III. Timing for the DDC112 in the Test Mode.

integration capacitors of both Input 1 and Input 2. This fixed

charge can be transferred to the integration capacitors either

once during an integration cycle or multiple times. In the case

where multiple packets are transferred during one integration

period, the 13pC charge is additive. This mode can be used

in both the continuous and noncontinuous mode timing. The

timing diagrams for test mode are shown in Figure 8. The top

three lines in Figure 8 define the timing when one packet of

13pC is sent to the integration capacitors. The bottom three

lines define the timing when multiple packets are sent to the

integration capacitors.

FIGURE 7. Frequency Response of the DDC112.

–10

–20

–30

–40

–50

0.1

INT

100

INT

Frequency

Integrate B

Action

CONV

TEST

Action

CONV

TEST

Integrate A

Test Mode Disabled

13pC into B

13pC into A

13pC into B

13pC into A

Test Mode Disabled

Test Mode Enabled

Integrate B

Integrate A

Integrate B

Integrate A

Test Mode Disabled

13pC into B

26pC into A

39pC into B

52pC into A

Test Mode Disabled

Test Mode Enabled

Integrate B

Integrate A

DDC112 Datasheet(PDF) 12 Page - Texas Instruments

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