DDC112 datasheet(13/37 Pages) TI2

13 / 37 page

DDC112

SBAS085B

www.ti.com

TEST and CONV work together to implement this feature.

The test mode is entered when TEST is HIGH prior to a

CONV edge. At that point, a CONV edge triggers the ground-

ing of the analog inputs and the switching of 13pC packets

of charge onto the integration capacitors. If TEST is kept

HIGH through at least two conversions (that is, a rise and fall

of CONV), all four integrators will be charged with a 13pC

packet. At the end of each conversion, the voltage at the

output of the integrators is digitized as discussed in the

Continuous and Non-Continuous Operational Modes section

of this data sheet. The test mode is exited when TEST is

LOW and a CONV edge occurs.

Once the test mode is entered as described above, TEST

can cycle as many times as desired. When this is done,

additional 13pC packets are added on the rising edge of

TEST to the existing charge on the integrator capacitors.

Multiple charge packets can be added in this way as long as

the TEST pin is not LOW when CONV toggles.

DIGITAL ISSUES

The digital interface of the DDC112 provides the digital results

via a synchronous serial interface consisting of a data clock

(DCLK), a transmit enable pin (DXMIT), a valid data pin

(DVALID), a serial data output pin (DOUT), and a serial data

input pin (DIN). The DDC112 contains only one A/D converter,

so the conversion process is interleaved between the two

inputs (see Figure 2). The integration and conversion process

is fundamentally independent of the data retrieval process.

Consequently, the CLK frequency and DCLK frequencies

need not be the same. DIN is used when multiple converters

are cascaded. Cascading or

daisy-chaining greatly simplifies

the interconnection and routing of the digital outputs in cases

where a large number of converters are needed. Refer to the

Cascading Multiple Converters section of this data sheet for

more detail.

The conversion rate of the DDC112 is set by a combination of

the integration time (determined by the user) and the speed of

the A/D conversion process. The A/D conversion time is

primarily a function of the system clock (CLK) speed. One

A/D conversion cycle encompasses the conversion of two

signals (one from each input of the DDC112) and reset time

for each of the integrators involved in the two conversions. In

most situations, the A/D conversion time is shorter than the

integration time. If this condition exists, the DDC112 will

operate in the continuous mode. When the DDC112 is in the

continuous mode, the sensor output is continuously integrated

by one of the two sides of each input.

In the event that the A/D conversion takes longer than the

integration time, the DDC112 will switch into a noncontinu-

ous mode. In noncontinuous mode, the A/D converter is not

able to keep pace with the speed of the integration process.

Consequently, the integration process is periodically halted

until the digitizing process catches up. These two basic

modes of operation for the DDC112—continuous and non-

continuous modes—are described in the

Continuous and

Noncontinuous Operational Modes section of this data sheet.

Continuous and Non-Continuous

Operational Modes

The state diagram of the DDC112 is shown in Figure 9. In all,

there are 8 states. Table IV provides a brief explanation of

each of the states.

Int A/Meas B

Cont

CONV • mbsy

CONV

Int B/Meas A

Cont

Ncont

Int A

Cont

Ncont

Int B

Cont

CONV

mbsy

FIGURE 9. State Diagram.

Four signals are used to control progression around the state

diagram: CONV and mbsy and their complements. The state

machine uses the level as opposed to the edges of CONV to

control the progression. mbsy is an internally-generated

signal not available to the user. It is active whenever a

measurement/reset/auto-zero (m/r/az) cycle is in progress.

STATE

MODE

DESCRIPTION

Ncont

Complete m/r/az of side A, then side B (if previous

state is state 4). Initial power-up state when CONV

is initially held HIGH.

Ncont

Prepare side A for integration.

Cont

Integrate on side A.

Cont

Integrate on side B; m/r/az on side A.

Cont

Integrate on side A; m/r/az on side B.

Cont

Integrate on side B.

Ncont

Prepare side B for integration.

Ncont

Complete m/r/az of side B, then side A (if previous

state is state 5). Initial power-up state when CONV

is initially held LOW.

TABLE IV. State Descriptions.

DDC112 Datasheet(PDF) 13 Page - Texas Instruments

DDC112 Datasheet(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

Datasheet Download

Link URL