LM46002PWPR datasheet(30/54 Pages) TI2

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LM46002

SNVSA13C – APRIL 2014 – REVISED APRIL 2019

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8.2.2.9 VCC Capacitor

The VCC pin is the output of an internal LDO for LM46002. The input for this LDO comes from either VIN or

BIAS (see Functional Block Diagram for LM46002). To insure stability of the part, place a minimum of 2.2-µF, 10-

V capacitor from this pin to ground.

8.2.2.10 BIAS Capacitors

For an output voltage of 3.3 V and greater, the BIAS pin can be connected to the output in order to increase light

load efficiency. This pin is an input for the VCC LDO. When BIAS is not connected, the input for the VCC LDO

will be internally connected into VIN. Because this is an LDO, the voltage differences between the input and

output will affect the efficiency of the LDO. If necessary, a capacitor with a value of 1 μF can be added close to

the BIAS pin as an input capacitor for the LDO.

8.2.2.11 Soft-Start Capacitors

The user can leave the SS/TRK pin floating, and the LM46002 will implement a soft-start time of 4.1 ms typically.

In order to use an external soft-start capacitor, size the capacitor such that the soft start time will be longer than

4.1 ms. Use Equation 23 to calculate the soft-start capacitor value:

where

•

CSS = soft-start capacitor value (µF)

•

ISSC = soft-start charging current (µA)

•

tSS = desired soft-start time (s)

(23)

For the desired soft start time of 10 ms and soft-start charging current of 2.2 µA, Equation 23 yield a soft start

capacitor value of 0.022 µF.

8.2.2.12 Undervoltage Lockout Setpoint

The undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and RENB. RENT

is connected between the VIN pin and the EN pin of the LM46002. RENB is connected between the EN pin and

the GND pin. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power

down or brown outs when the input voltage is falling. The following equation can be used to determine the VIN

UVLO level.

VIN-UVLO-RISING = VENH × (RENB + RENT) / RENB

(24)

The EN rising threshold (VENH) for LM46002 is set to be 2.1 V (typical). Choose the value of RENB to be 1 MΩ to

minimize input current from the supply. If the desired VIN UVLO level is at 5 V, then the value of RENT can be

calculated using Equation 25:

RENT = (VIN-UVLO-RISING / VENH – 1) × RENB

(25)

Equation 25 yields a value of 1.38 MΩ. The resulting falling UVLO threshold, equals 4.3 V, can be calculated by

below equation, where EN falling threshold (VENL) is 1.8 V (typical).

VIN-UVLO-FALLING = VENL × (RENB + RENT) / RENB

(26)

8.2.2.13 PGOOD

A typical pull-up resistor value is 10 k

Ω to 100 kΩ from the PGOOD pin to a voltage no higher than 12 V. If it is

desired to pull up the PGOOD pin to a voltage higher than 12 V, a resistor can be added from the PGOOD pin to

ground to divide the voltage seen by the PGOOD pin to a value no higher than 12 V.

LM46002PWPR Datasheet(PDF) 30 Page - Texas Instruments

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