LM76005RNPR datasheet(4/51 Pages) TI2

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Pin Functions

I/O(1)

DESCRIPTION

NO.

NAME

1, 2, 3, 4, 5

Switching output of the regulator. Internally connected to the source of the HS FET and

drain of the LS FET. Connect to power inductor and bootstrap capacitor.

BOOT

Bootstrap capacitor connection for high-side driver. Connect a high-quality 470-nF capacitor

from this pin to the SW pin.

7, 19, 23, 27,

28, 29, 30

—

Not internally connected. Connect pins 19, 27, 28, 29, and 30 to ground copper on PCB to

improve heat-sinking of the device and board level reliability. Leave pins 7 and 23 floating in

order to maximize distance from the high voltage input to ground.

VCC

Output of internal bias supply. Used as supply to internal control circuits. Connect a high-

quality 2.2-µF capacitor from this pin to GND. TI does not recommended loading this pin by

external circuitry.

BIAS

Optional BIAS LDO supply input. TI recommends tying this to VOUT when 3.3 V ≤ VOUT ≤ 18

V, or tying to an external 3.3-V or 5-V rail if available, to improve efficiency. When used,

place a 1-µF capacitor from this terminal to ground. Tie to ground when not in use.

Switching frequency setting pin. Place a resistor from this pin to ground to set the switching

frequency. If floating, the default switching frequency is 400 kHz. Do not short to ground.

SS/TRK

Soft-start control pin. Leave this pin floating to use the 6.3-ms internal soft-start ramp. An

external capacitor can be connected from this pin to ground to extend the soft-start time. A

2-µA current sourced from this pin can charge the capacitor to provide the ramp. Connect to

external ramp for tracking. Do not short to ground.

Feedback input for output voltage regulation. Connect a resistor divider to set the output

voltage. Never short this terminal to ground during operation.

PGOOD

Open-drain power-good flag output. Connect to suitable voltage supply through a current

limiting resistor. High = VOUT regulation OK, Low = VOUT regulation fault. PGOOD = Low

when EN = Low

SYNC/MODE

Synchronization input and mode setting pin. Do not float, tie to ground if not used.

Tie to ground: DCM/PFM operation under light loads, improved efficiency

Tie to logic high: forced PWM under light loads, constant switching frequency over load

Tie to external clock source: synchronize switching action to the clock, forced PWM under

light loads.

Triggers on the rising edge of external clock.

Precision-enable input to regulator. Do not float. High = on, Low = off. Can be tied to VIN.

Precision-enable input allows adjustable UVLO by external resistor divider.

13, 14, 15

AGND

Analog ground. Ground reference for internal references and logic. All electrical parameters

are measured with respect to this pin. Connect to system ground on PCB.

20, 21, 22

PVIN

Supply input to internal bias LDO and HS FET. Connect to input supply and input bypass

capacitors CIN. CIN must be placed right next to this pin and PGND and connected with

short traces.

24, 25, 26

PGND

Power ground, connected to the source of LS FET internally. Connect to system ground,

DAP/EP, AGND, and ground side of CIN and COUT. Path to CIN must be as short as

possible.

DAP

—

Low impedance connection to AGND. Connect to system ground on PCB. Major heat

dissipation path for the die. Must be used for heat sinking by soldering to ground copper on

PCB. Thermal vias are preferred.

(1)

A = Analog, O = Output, I = Input, G = Ground, P = Power

LM76005

SNVSBK5A – FEBRUARY 2020 – REVISED JULY 2020

www.ti.com

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