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ONET1130EC Datasheet(PDF) 43 Page - Texas Instruments |
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ONET1130EC Datasheet(HTML) 43 Page - Texas Instruments |
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43 / 64 page ![]() ONET1130EC www.ti.com SLLSEJ3A – JUNE 2015 – REVISED JULY 2015 8.6.3.10 TX Register 19 (offset = 0000 0000) [reset = 0h] Figure 60. TX Register 19 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22. TX Register 19 Field Descriptions Bit Field Type Reset Description 7 TXFD_MOD1 R/W 0 TX frequency detection mode selection 00 = auto selection enabled 01 = Pre-selected to 10.3Gbps 6 TXFD_MOD0 R/W 0 10 = Pre-select to 11.1Gbps 11 = test mode (do not use) TX frequency detector enable bit 5 TXFD_EN R/W 0 1 =TX frequency detector is always enabled 0 = TX frequency detector in automatic mode TX frequency detector disable bit 4 TXFD_DIS R/W 0 1 = TX frequency detector is always disabled 0 = TX frequency detector is in automatic mode TX CDR fast lock disable bit 3 TXFL_DIS R/W 0 1 = TX CDR fast lock disabled 0 = TX CDR in fast lock mode 2 TXDIV2 R/W 0 TX Divider Ratio 000: Full-Rate, 1 TXDIV1 R/W 0 001: Divide by 2 010: Divide by 4 011: Divide by 8 0 TXDIV0 R/W 0 100: Divide by 16 101: Divide by 32 Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 43 Product Folder Links: ONET1130EC |
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