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ONET1130EC Datasheet(PDF) 46 Page - Texas Instruments |
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ONET1130EC Datasheet(HTML) 46 Page - Texas Instruments |
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46 / 64 page ![]() ONET1130EC SLLSEJ3A – JUNE 2015 – REVISED JULY 2015 www.ti.com 8.6.5.3 RX Registers 42 (offset = 0000 0000) [reset = 0h] Figure 64. RX Registers 42 7 6 5 4 3 2 1 0 0 0 0 0 Reserved R R R R R R R R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; RCLR = Read clear Table 26. RX Registers 42 Field Descriptions Bit Field Type Reset Description RX CDR lock status bit 7 RXCDRLock R 0 1 = RX CDR is not locked 0 = RX CDR is locked Latched low status of bit 7. Cleared when read. 6 RXCDRlock (latched LOW) RCLR 0 Latched low bit set to 0 when raw status goes low and keep it low even if raw status goes high. RX LOS status bit 5 RXLOS R 0 1 = RX LOS asserted 0 = RX LOS de-asserted Latched high status of RXLOS(bit5). Cleared when read. 4 RX_LOS (latched high) RCLR 0 Latched high status set to 1 when raw status goes high and keep it high even if raw status goes low. 3:0 – R 0 Reserved 46 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ONET1130EC |
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