2

Integrated

Circuit

Systems, Inc.

ICS9214

0809F—11/05/07

Pin Descriptions

PIN #

PIN NAME

PIN TYPE

DESCRIPTION

1

AVDD2.5

PWR

2.5V Analog Power pin for Core PLL

2

AGND

PWR

Analog Ground pin for Core PLL

3IREFY

IN

This pin establishes the reference current for the differential clock

pairs. This pin requires a fixed precision resistor tied to ground in

order to establish the appropriate current.

4

AGND

PWR

Analog Ground pin for Core PLL

5

CLK_INT

IN

"True" reference clock input.

6

CLK_INC

IN

"Complementary" reference clock input.

7

VDD2.5

PWR

Power supply, nominal 2.5V

8

GND

PWR

Ground pin.

9SMBCLK

IN

Clock pin of SMBUS circuitry, 5V tolerant

10

SMBDAT

I/O

Data pin of SMBUS circuitry, 5V tolerant

11

OE

IN

Active high input for enabling outputs.

0 = tri-state outputs, 1= enable outputs

12

SMB_A0

IN

SMBus address bit 0 (LSB)

13

SMB_A1

IN

SMBus address bit 1

14

BYPASS#/PLL

IN

Input to select Bypass(fan-out) or PLL (ZDB) mode

0 = Bypass mode, 1= PLL mode

15

VDD2.5

PWR

Power supply, nominal 2.5V

16

ODCLK_C3

OUT

"Complementary" side of open drain differential clock output. This

open drain output needs an external resistor network..

17

ODCLK_T3

OUT

"True" side of open drain differential clock output. This open drain

output needs an external resistor network..

18

GND

PWR

Ground pin.

19

ODCLK_C2

OUT

"Complementary" side of open drain differential clock output. This

open drain output needs an external resistor network..

20

ODCLK_T2

OUT

"True" side of open drain differential clock output. This open drain

output needs an external resistor network..

21

GND

PWR

Ground pin.

22

VDD2.5

PWR

Power supply, nominal 2.5V

23

ODCLK_C1

OUT

"Complementary" side of open drain differential clock output. This

open drain output needs an external resistor network..

24

ODCLK_T1

OUT

"True" side of open drain differential clock output. This open drain

output needs an external resistor network..

25

GND

PWR

Ground pin.

26

ODCLK_C0

OUT

"Complementary" side of open drain differential clock output. This

open drain output needs an external resistor network..

27

ODCLK_T0

OUT

"True" side of open drain differential clock output. This open drain

output needs an external resistor network..

28

VDD2.5

PWR

Power supply, nominal 2.5V