±IN

+IN

V±

VS+

GND

VS±

GND

VOUT

VIN

Run the input traces

as far away from

the supply lines

as possible.

Use a low-ESR,

ceramic bypass

capacitor.

RF

RG

Place components

close to the device

and to each other to

reduce parasitic

errors.

Use a low-ESR,

ceramic bypass

capacitor.

OUT

V+

Copyright © 2016, Texas Instruments Incorporated

19

TLV316-Q1, TLV2316-Q1, TLV4316-Q1

www.ti.com

SBOS845B – NOVEMBER 2016 – REVISED AUGUST 2017

Product Folder Links: TLV316-Q1 TLV2316-Q1 TLV4316-Q1

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Copyright © 2016–2017, Texas Instruments Incorporated

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the

operational amplifier. Bypass capacitors reduce the coupled noise by providing low-impedance power

sources local to the analog circuitry.

–

Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

Separate grounding for analog and digital portions of the circuitry is one of the simplest and most

effective methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to

ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to

physically separate digital and analog grounds, paying attention to the flow of the ground current. For

more detailed information, see Circuit Board Layout Techniques.

•

To reduce parasitic coupling, run the input traces as far away from the supply or output traces as

possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much

better than crossing in parallel with the noisy trace.

•

Place the external components as close to the device as possible. Keeping RF and RG close to the

inverting input minimizes parasitic capacitance, as shown in Figure 18.

•

Keep the length of input traces as short as possible. Remember that the input traces are the most

sensitive part of the circuit.

•

Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly

reduce leakage currents from nearby traces that are at different potentials.

11.2 Layout Example

Figure 18. Operational Amplifier Board Layout for a Noninverting Configuration