6.6 I2C Interface Timing

see the Timing Diagrams and Two-Wire Timing Diagrams sections for additional information (unless otherwise noted)(1)

FAST MODE

HIGH-SPEED

MODE

UNIT

MIN

MAX

MIN

MAX

f(SCL)

SCL operating frequency

1

400

1

2380

kHz

t(BUF)

Bus-free time between STOP and START conditions

1.3

0.16

µs

t(SUSTA) Repeated START condition setup time

0.6

0.16

µs

t(HDSTA)

Hold time after repeated START condition.

After this period, the first clock is generated.

0.6

0.16

µs

t(SUSTO) STOP condition setup time

0.6

0.16

µs

t(HDDAT) Data hold time

4

900

4

120

ns

t(SUDAT) Data setup time

100

20

ns

t(LOW)

SCL clock low period

1.3

0.28

µs

t(HIGH)

SCL clock high period

0.6

0.06

µs

tRC

Clock rise time

300

40

ns

tRC

Clock rise time for SCLK ≤ 100 kHz

1000

ns

tF

Clock fall time

300

40

ns

ttimeout

Timeout (SCL = GND or SDA = GND) TMP175

25

74

25

74

ms

ttimeout

Timeout (SCL = GND or SDA = GND) TMP75

20

30

20

30

(1)

Compatible with standard mode timings

TMP175, TMP75

SBOS288M – JANUARY 2004 – REVISED DECEMBER 2020

www.ti.com

6

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