TMS320F28062F datasheet(27/204 Pages) TI2

27 / 204 page

Following are other methods to reduce power consumption further:

• The flash module may be powered down if code is run off SARAM. This results in a current reduction of 18

mA (typical) in the VDD rail and 13 mA (typical) in the VDDIO rail.

• Savings in IDDIO may be realized by disabling the pullups on pins that assume an output function.

• To realize the lowest VDDA current consumption in a low-power mode, see the respective analog chapter of

the TMS320x2806x Technical Reference Manual to ensure each module is powered down as well.

• Power savings can be achieved by powering down the flash. This must be done by code running off RAM

(not flash).

7.5.3 Current Consumption Graphs (VREG Enabled)

100

150

200

250

SYSCLKOUT (MHz)

IDDIO

IDDA

IDD3VFL

Total

Figure 7-1. Typical Operational Current (Flash) Versus Frequency (Internal VREG)

100

200

300

400

500

600

700

800

900

SYSCLKOUT (MHz)

Figure 7-2. Typical Operational Power Versus Frequency (Internal VREG)

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TMS320F28062, TMS320F28062F

SPRS698J – NOVEMBER 2010 – REVISED SEPTEMBER 2021

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TMS320F28062F Datasheet(PDF) 27 Page - Texas Instruments